EPC21C20U vs EPC1LI20 Perbandingan
Perbandingan bersamaan detil EPC21C20U dari Intel dan EPC1LI20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC21C20U | EPC1LI20 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Aktif | Obsolete |
| Manufacturer | Intel / Altera | — |
| Product Type | Configuration Device (Boot Flash) | — |
| Ukuran Memori | 20 Mbit (2.5 Mbyte) | 1 Mb (1,048,576 bits) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | 5.0 V (4.75 V to 5.25 V) |
| Antarmuka | Altera/Intel Passive Serial (PS) and Active Serial (AS), JTAG (IEEE 1149.1) | — |
| Paket | 20-pin UBGA (Ultra FineLine BGA) - also called 20-pin FBGA | 20-pin PLCC (J-lead, 9x9 mm) |
| In-System Programmability | Yes (via JTAG) | — |
| Bitstream Compression Support | Yes | — |
| Cascade (Multi-Device) Support | Yes (nCASC daisy-chain) | — |
| Supported FPGA Families | APEX II, APEX 20KE, APEX 20KC, Mercury, Stratix, Cyclone, ACEX 1K, FLEX 10KE | — |
| Suhu Kerja | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature range] |
| Tipe Mounting | Surface Mount (BGA) | Surface Mount (PLCC socket compatible) |
| Status RoHS | Compliant (per Intel/Altera product page) | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Lead-Free | Yes | — |
| Configuration Mode | Passive Serial (PS) / Active Serial (AS) via FPGA controller | — |
| Tipe Memori | — | OTP Configuration PROM (EPROM-based) |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Jumlah Pin | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Level MSL | — | 1 (per Partstack datasheet record) |