EPC2LC20NA vs EPC1LI20 Perbandingan
Perbandingan bersamaan detil EPC2LC20NA dari Altera dan EPC1LI20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2LC20NA | EPC1LI20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Manufacturer | Altera Corporation (Intel Programmable Solutions Group) | — |
| Tipe Memori | Configuration PROM (Flash-based, ISP) | OTP Configuration PROM (EPROM-based) |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Antarmuka | Serial (passive-serial) data output to FPGA | — |
| Programmability | In-system programmable via IEEE 1532 JTAG | — |
| Paket | 20-pin PLCC (9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Tipe Mounting | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Suhu Kerja | -40C to +85C (industrial grade) | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury | — |
| JTAG Compliance | IEEE Std 1149.1 / IEEE 1532 | — |
| Configuration Mode | Passive Serial (PS) | — |
| Status RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - original Altera part may be non-RoHS SnPb finish] |
| Daisy-Chain Support | Yes | — |
| Recommended Companion FPGA | Altera Cyclone, FLEX 10K, APEX 20K series | — |
| Ukuran Memori | — | 1 Mb (1,048,576 bits) |
| Configuration Interface | — | Altera Passive Serial / Altera Active Serial / JTAG (IEEE 1149.1) |
| Maximum Configuration Clock | — | 8 MHz |
| Supply Voltage (VCC) | — | 5.0 V (4.75 V to 5.25 V) |
| Programming Voltage (VPP) | — | 12.75 V (typical, factory-programmed via JTAG) |
| Jumlah Pin | — | 20 |
| Cascading Support | — | Yes (nCASC pin for multi-device daisy chain) |
| Endurance | — | OTP (one-time programmable, 1000 erase-equivalent UV cycles for pre-program erase) |
| JTAG Programming | — | Yes (in-system via IEEE 1149.1) |
| Compatible FPGA Families | — | FLEX 8000, FLEX 10K, ACEX 1K, APEX 20K, Mercury |
| Level MSL | — | 1 (per Partstack datasheet record) |