EPC2LI20 vs EPC20LI20N Perbandingan

Perbandingan bersamaan detil EPC2LI20 dari Altera dan EPC20LI20N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2LI20 EPC20LI20N
Merek Altera Intel
Kategori Memory ICs FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Ukuran Memori 1.6 Mb (1,572,864 bits) 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte)
Tipe Memori Flash (in-system programmable) EPROM (UV-erasable, in-system programmable)
Programmable Type In System Programmable (ISP) —
Fungsi Configuration PROM for SRAM-based FPGAs —
Supply Voltage - Operating 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) —
Suhu Kerja -40 C to +85 C (Industrial) -40C to +85C (industrial)
Paket / Case 20-PLCC (J-lead, 9x9 mm) —
Tipe Mounting Surface Mount (PLCC socket-compatible) Surface Mount (PLCC socket or direct solder)
Configuration Interface Serial or Byte-wide (parallel) —
Decompression On-chip (supports compressed bitstreams) —
JTAG / ISP Interface IEEE 1532 (TCK, TMS, TDI, TDO) —
Multi-Device Support Yes (daisy-chain configuration) —
User-Accessible Memory Yes (unused flash available to user logic) —
Status RoHS [DATA_NEEDED: RoHS status] —
Level MSL [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Antarmuka — Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS)
Tegangan Pemuat — 3.3 V (5.0 V compatible variant in same family)
Configuration Clock — Up to 10 MHz
Target FPGA Families — APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA
Paket — 20-pin PLCC (9x9 mm, JEDEC MS-018)
Programming Interface — IEEE 1532 / JTAG (in-system)
Standby Current — [DATA_NEEDED: standby current uA]
Active Configuration Current — [DATA_NEEDED: ICC active mA]
Programming Voltage — [DATA_NEEDED: VPP]
Programming Cycles — [DATA_NEEDED: endurance cycles]
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Multi-Device Daisy-Chain — Supported via nCASC pin

Spek dan Sumber

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