EPC2LI20 vs EPC20LI20N 比較
詳細並排比較 EPC2LI20 由 Altera 與 EPC20LI20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LI20 | EPC20LI20N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| 記憶體容量 | 1.6 Mb (1,572,864 bits) | 1.6 Mbit (65,536 x 1-bit words, approx. 200 Kbyte) |
| 記憶體類型 | Flash (in-system programmable) | EPROM (UV-erasable, in-system programmable) |
| Programmable Type | In System Programmable (ISP) | — |
| 功能 | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| 工作溫度 | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| 封裝 / 外殼 | 20-PLCC (J-lead, 9x9 mm) | — |
| 安裝類型 | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC socket or direct solder) |
| Configuration Interface | Serial or Byte-wide (parallel) | — |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| 介面 | — | Serial (4-pin Altera Passive Serial: DCLK, DATA0, nCONFIG, nSTATUS) |
| 供應電壓 | — | 3.3 V (5.0 V compatible variant in same family) |
| Configuration Clock | — | Up to 10 MHz |
| Target FPGA Families | — | APEX II, APEX 20K/KC/KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| 封裝 | — | 20-pin PLCC (9x9 mm, JEDEC MS-018) |
| Programming Interface | — | IEEE 1532 / JTAG (in-system) |
| Standby Current | — | [DATA_NEEDED: standby current uA] |
| Active Configuration Current | — | [DATA_NEEDED: ICC active mA] |
| Programming Voltage | — | [DATA_NEEDED: VPP] |
| Programming Cycles | — | [DATA_NEEDED: endurance cycles] |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Multi-Device Daisy-Chain | — | Supported via nCASC pin |