EPC2LS20U vs EPC2LI20 Perbandingan

Perbandingan bersamaan detil EPC2LS20U dari Altera dan EPC2LI20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2LS20U EPC2LI20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup Obsolete NRND
Product Type In-System Programmable Configuration PROM —
Memory Density 1.6 Mbit —
Operating Voltage (VCC) 3.3 V —
Antarmuka Altera serial configuration / JTAG —
Programming Method In-System Programmable (ISP) via JTAG —
Paket 20-PLCC (J-lead, 9x9 mm) —
Lead-Free / RoHS Yes (per "U" suffix) —
Suhu Kerja [DATA_NEEDED: Operating Temperature] -40 C to +85 C (Industrial)
Supported FPGA Families Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 —
Configuration Modes PS (Passive Serial), AS, FPP —
JTAG Support Yes (IEEE 1149.1 boundary scan) —
Done Pin Yes (open-drain programmable polarity) —
nSTATUS Pin Yes (open-drain error flag) —
nCONFIG Pin Yes (reset/reconfiguration input) —
DCLK Output Yes (configuration clock to FPGA) —
Level MSL [DATA_NEEDED: MSL Level] [DATA_NEEDED: MSL level]
Compliance RoHS (Pb-free per U suffix) —
Ukuran Memori — 1.6 Mb (1,572,864 bits)
Tipe Memori — Flash (in-system programmable)
Programmable Type — In System Programmable (ISP)
Fungsi — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Paket / Case — 20-PLCC (J-lead, 9x9 mm)
Tipe Mounting — Surface Mount (PLCC socket-compatible)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)
Status RoHS — [DATA_NEEDED: RoHS status]

Spek dan Sumber

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