EPC2XXA vs EPC2LS20U Perbandingan

Perbandingan bersamaan detil EPC2XXA dari Altera dan EPC2LS20U dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2XXA EPC2LS20U
Merek Altera Altera
Kategori FPGA & CPLD Memory ICs
Status Lingkungan Hidup NRND Obsolete
Tipe Memori Configuration Flash (PROM) —
Ukuran Memori 1.6 Mbit —
Configuration Interface Passive Serial (PS) / Active Serial (AS) —
Maximum Configuration Clock 33 MHz —
JTAG Support IEEE 1149.1 Boundary-Scan (ISP) Yes (IEEE 1149.1 boundary scan)
Operating Voltage (VCC) 3.0 V to 3.6 V 3.3 V
Operating Voltage (VCCJ) 1.8 V / 2.5 V / 3.3 V —
Suhu Kerja -40 C to +85 C (industrial) [DATA_NEEDED: Operating Temperature]
Paket 20-pin SOIC (SO-20) 12.8 mm x 7.5 mm 20-PLCC (J-lead, 9x9 mm)
Tipe Mounting Surface Mount —
Cascadable Yes (daisy-chain multiple devices) —
Programmer Quartus II / Quartus Prime Programmer —
Compatible FPGA Families Cyclone, Cyclone II, Cyclone III, MAX II, MAX V, Stratix (selected) —
Status RoHS Compliant —
Lead-Free Yes —
Product Type — In-System Programmable Configuration PROM
Memory Density — 1.6 Mbit
Antarmuka — Altera serial configuration / JTAG
Programming Method — In-System Programmable (ISP) via JTAG
Lead-Free / RoHS — Yes (per "U" suffix)
Supported FPGA Families — Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000
Configuration Modes — PS (Passive Serial), AS, FPP
Done Pin — Yes (open-drain programmable polarity)
nSTATUS Pin — Yes (open-drain error flag)
nCONFIG Pin — Yes (reset/reconfiguration input)
DCLK Output — Yes (configuration clock to FPGA)
Level MSL — [DATA_NEEDED: MSL Level]
Compliance — RoHS (Pb-free per U suffix)

Spek dan Sumber

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