EPM5064JI-1 vs EPM5064LC-2 Perbandingan

Perbandingan bersamaan detil EPM5064JI-1 dari Intel dan EPM5064LC-2 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM5064JI-1 EPM5064LC-2
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 64 64
User I/O Pins [DATA_NEEDED: user I/O count from datasheet] —
Paket 68-pin PLCC (windowed ceramic) PLCC-44 (J-Lead, plastic)
Logic Elements [DATA_NEEDED: total logic elements] —
Propagation Delay (tPD) [DATA_NEEDED: combinational tPD from datasheet] 45 ns
Tegangan Pemuat 5 V —
Suhu Kerja [DATA_NEEDED: commercial vs industrial grade temp range] -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
Process Technology CMOS, UV-erasable CMOS, OTP EPROM (UV-erasable base)
Speed Grade JI-1 (commercial, -10/-12/-15 family) —
Programmability UV-erasable (windowed package) —
Data Retention 25 years (per MAX 5000 datasheet) —
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: not stated in provided data] [DATA_NEEDED: not specified in source]
Device Family — MAX 5000
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 4
Logic Elements per LAB — 16
Number of Inputs — 36 (7 dedicated + 28 I/O)
Number of I/O Pins — 28
Number of Flip-Flops — 28
Maximum Internal Frequency — 40 MHz
Programmable Polarity — Yes
Programmable Output Enable — Yes, per macrocell
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Programming Method — Altera byte-wide / JTAG programmer

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