EPM5128GC-2 vs EPM5128GC2 Perbandingan
Perbandingan bersamaan detil EPM5128GC-2 dari Altera dan EPM5128GC2 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5128GC-2 | EPM5128GC2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Macrocells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | Approx. 25 ns (typical, -2 speed grade) | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Package Type | 68-pin PGA (Pin Grid Array) | — |
| Package Code (per Partstack) | WPGA | — |
| Number of Terminals | 68 | — |
| Programming Technology | UV-erasable EPROM | — |
| Suhu Kerja | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Grade (per Partstack) | COMMERCIAL | — |
| Terminal Form | PIN/PEG | — |
| Configuration Memory | Non-volatile, one-time programmable (erasable via UV) | On-chip EPROM (no external boot device) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | — | 128 |
| Usable Gates | — | 2.5K |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum Internal Frequency | — | 50 MHz |
| Supply Voltage VCC | — | 5 V |
| I/O Pins | — | 64 |
| Dedicated Inputs | — | 16 |
| Paket | — | Ceramic PGA (GC, windowed) |
| Programmable Flip-Flop Modes | — | D / T / JK / SR (selectable) |
| Architecture | — | AND/OR plane + programmable macro cell + PIA |
| Process Technology | — | CMOS EPROM |
| Reprogrammability | — | UV-erasable (windowed ceramic package) |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |
| Jumlah Pin | — | [DATA_NEEDED: total PGA pin count] |