EPM5128GM883B vs EPM5128JC Perbandingan
Perbandingan bersamaan detil EPM5128GM883B dari Altera dan EPM5128JC dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5128GM883B | EPM5128JC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV EPLD (Erasable Programmable Logic Device) | EPLD / CPLD |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/O Pins | 52 | [DATA_NEEDED: user I/O pin count] |
| Dedicated Inputs | 7 | 8 |
| Propagation Delay (tpd) | 55 ns | — |
| External Clock Inputs | 1 | — |
| Technology | CMOS | — |
| Configuration Memory | UV-erasable EPROM | UV-erasable EPROM (windowed package) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Paket | PGA-883 (ceramic pin grid array) | — |
| Suhu Kerja | -55C to +125C (military) | Commercial 0C to +70C |
| Qualification | MIL-STD-883 Class B (suffix 883B) | — |
| Program/Erase Method | UV-erasable | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 35 ns |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Jumlah Pin | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Tipe Mounting | — | Surface Mount (PLCC socket or solder) |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| Status RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |