EPM5128GM883B vs EPM5128JC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GM883B sa pamamagitan ng Altera at EPM5128JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128GM883B | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV EPLD (Erasable Programmable Logic Device) | EPLD / CPLD |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/O Pins | 52 | [DATA_NEEDED: user I/O pin count] |
| Dedicated Inputs | 7 | 8 |
| Propagation Delay (tpd) | 55 ns | — |
| External Clock Inputs | 1 | — |
| Technology | CMOS | — |
| Configuration Memory | UV-erasable EPROM | UV-erasable EPROM (windowed package) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | PGA-883 (ceramic pin grid array) | — |
| Temperature na Operasyon | -55C to +125C (military) | Commercial 0C to +70C |
| Qualification | MIL-STD-883 Class B (suffix 883B) | — |
| Program/Erase Method | UV-erasable | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 35 ns |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Bilang ng Pins | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Uri ng Pagpapasok | — | Surface Mount (PLCC socket or solder) |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status - legacy part] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |