EPM5192AGC vs EPM5192AGC84-20 Perbandingan
Perbandingan bersamaan detil EPM5192AGC dari Altera dan EPM5192AGC84-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5192AGC | EPM5192AGC84-20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | CMOS |
| Paket | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | — |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tegangan Pemuat | [DATA_NEEDED: VCC nominal and tolerance] | [DATA_NEEDED: VCC range] |
| Tipe Mounting | Through-hole (Pin Grid Array) | Through-Hole (Pin Grid Array socket) |
| Status RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| I/O Standard | — | 5V CMOS / TTL compatible |