EPM5192LC-25 vs EPM5192LC1 Perbandingan

Perbandingan bersamaan detil EPM5192LC-25 dari Altera dan EPM5192LC1 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM5192LC-25 EPM5192LC1
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
Paket JLCC-84 (ceramic J-lead chip carrier) PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier)
Tipe Mounting Surface Mount Surface Mount
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) —
Suhu Kerja 0C to +70C (commercial) —
Tegangan Pemuat 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) —
Manufacturer Altera Corporation (now Intel PSG) —
Status RoHS Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status]
Device Type — Complex PLD (CPLD), UV-erasable/OTP
Equivalent Gates — 3750
Dedicated Inputs — 7
User I/O Pins — 64
Nominal Supply Voltage (VCC) — 5 V
Supply Voltage Range — 4.75 V to 5.25 V
Frekuensi Bawah Maximum — 50 MHz
Propagation Delay (tPD) — 40 ns
Process Technology — CMOS EPROM
Programming Method — OTP (LC plastic package); UV-erasable equivalents in JC ceramic package
Operating Temperature (Commercial 'LC') — 0 °C to 70 °C
JEDEC Package Code — S-PQCC-J84

Spek dan Sumber

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