EPM7128SQI100-10 vs EPM7128SQC100-10N Perbandingan
Perbandingan bersamaan detil EPM7128SQI100-10 dari Altera dan EPM7128SQC100-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoletePerbandingan Spesifikasi
| Parameter Umum | EPM7128SQI100-10 | EPM7128SQC100-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Aktif |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Blocks (LABs) | 8 (16 macrocells each) | — |
| Package Type | PQFP-100 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 125 MHz to 250 MHz | — |
| Counter Speed | Up to 175.4 MHz | — |
| Operating Voltage (VCC) | 5 V | — |
| Suhu Kerja | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Program/Erase Cycles | 100 minimum | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Logic Family | CMOS | — |
| I/O Compatibility | TTL-compatible, 5V/3.3V multi-voltage | — |
| Status RoHS | [DATA_NEEDED: RoHS status not in provided data] | — |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| User I/O Pins | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (MultiVolt interface) |
| Paket | — | 100-pin PQFP (BQFP) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), 4-pin |
| Tipe Mounting | — | Surface Mount |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| Architecture Generation | — | Second-generation MAX |