EPM9320ALC84-20 vs EPM9320LC84-15 Perbandingan

Perbandingan bersamaan detil EPM9320ALC84-20 dari Altera dan EPM9320LC84-15 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9320ALC84-20 EPM9320LC84-15
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 9000 MAX 9000
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 320
Logic Array Blocks (LABs) 16 20
Maximum User I/Os 212 —
Pin-to-Pin Delay (tPD) 20 ns —
Paket PLCC-84 84-pin PLCC (Plastic Leaded Chip Carrier)
Process Technology 0.5 µm CMOS EEPROM —
Tegangan Pemuat 5.0 V —
Programmability In-system via IEEE 1149.1 JTAG 5.0 V in-system programmable (ISP) via JTAG
Suhu Kerja [DATA_NEEDED: commercial or industrial grade] -40C to +85C (commercial) [DATA_NEEDED: exact grade]
Tipe Mounting Surface Mount (PLCC socket compatible) Surface Mount
Configuration Memory Non-volatile EEPROM —
Boundary Scan JTAG IEEE 1149.1 —
Design Software MAX+PLUS II / Quartus II (legacy) —
Status RoHS [DATA_NEEDED: per Altera datasheet] [DATA_NEEDED: confirm from manufacturer]
Series — EPM9320
Usable Gates — 6,000
Propagation Delay (tPD) — 15 ns (max)
Frekuensi Bawah Maximum — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
JTAG Interface — IEEE Std. 1149.1 boundary-scan compliant
Technology — CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

Spek dan Sumber

Buka Semua Produk Buat BOM Ajukan Diskon