EPM9320ALC84-20 vs EPM9320LC84-15 比較
詳細並排比較 EPM9320ALC84-20 由 Altera 與 EPM9320LC84-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320ALC84-20 | EPM9320LC84-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| 封裝 | PLCC-84 | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| 供應電壓 | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | 5.0 V in-system programmable (ISP) via JTAG |
| 工作溫度 | [DATA_NEEDED: commercial or industrial grade] | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS 狀態 | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Usable Gates | — | 6,000 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| 最大時脈頻率 | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |