EPM9560RC-15 vs EPM9560R1208-20 Perbandingan

Perbandingan bersamaan detil EPM9560RC-15 dari Altera dan EPM9560R1208-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC-15 EPM9560R1208-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 560 560
Usable Gates 12,000 6,000
Logic Array Blocks (LABs) 16 (40 macrocells each) —
Maximum User I/O Pins 191 —
Pin-to-Pin Delay (tPD1) 15 ns —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) —
Suhu Kerja 0 C to +70 C (commercial) 0C to +70C (commercial)
Paket 240-pin RQFP (32x32 mm) R-1208 (BGA-style fine-pitch)
Tipe Mounting Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm via current distributor data]
In-System Programmability Yes (5.0 V ISP via JTAG) Yes (IEEE 1149.1 JTAG)
Logic Array Blocks — 52 (typical for 560 macrocells)
Maximum User I/O — 212
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

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