MPC8535EAVTATH vs MPC8536EAVTAQG Perbandingan
Perbandingan bersamaan detil MPC8535EAVTATH dari NXP Semiconductors dan MPC8536EAVTAQG dari NXP Semiconductors. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
NXP Semiconductors
MPC8535EAVTATH - PowerPC e500 MPU 1.25GHz 783-FCPBGA | NXP
MPC8535EAVTATH ✓ AktifNXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndPerbandingan Spesifikasi
| Parameter Umum | MPC8535EAVTATH | MPC8536EAVTAQG |
|---|---|---|
| Merek | NXP Semiconductors | NXP Semiconductors |
| Kategori | Microcontrollers | Microcontrollers |
| Status Lingkungan Hidup | Aktif | NRND |
| Core Architecture | PowerPC e500 | — |
| Processor Series | MPC85xx PowerQUICC III | MPC85xx (PowerQUICC III) |
| Number of Cores | 1 | 1 |
| Lebar Bus Data | 32-bit | 32 bit |
| Maximum Core Frequency | 1.25 GHz | — |
| Package Type | 783-FCPBGA (29x29 mm) | — |
| Tegangan Pemuat | 1.0 V core / 1.5 V, 1.8 V, 2.5 V, 3.3 V I/O | [DATA_NEEDED: core/IO supply voltage] |
| Process Technology | 90 nm CMOS | — |
| Suhu Kerja | 0C to +105C (TJ) [DATA_NEEDED: full ambient range] | [DATA_NEEDED: operating temperature range] |
| Tipe Mounting | Surface Mount (BGA) | Surface Mount (BGA) |
| Lead-Free | Yes [DATA_NEEDED: confirm RoHS] | — |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL rating] | — |
| Memory Controller | DDR/DDR2 SDRAM | — |
| Ethernet Controllers | Dual Gigabit Ethernet with TCP/IP acceleration | — |
| Security Engine | Integrated IPsec / SSL / TLS / bulk crypto accelerator | — |
| Programmable Engine | QUICC Engine subsystem | — |
| Core | — | PowerPC e500, 32-bit |
| Frekuensi Bawah Maximum | — | 1.0 GHz |
| Paket | — | 783-FCPBGA (29x29 mm) |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| Level MSL | — | [DATA_NEEDED: MSL rating] |
| Status RoHS | — | [DATA_NEEDED: RoHS compliance] |