Intel

EPM9560RC240-15 - MAX 9000 CPLD 560 Macro Cells | Intel

MPN: EPM9560RC240-15 ✗ Akhir Hidup
5.0 V Vdss 240-pin RQFP (32x32 mm) with exposed pad Package 145 MHz Speed
MOQ: 1 |

EPM9560RC240-15 Ringkasan

The Intel (Altera) EPM9560RC240-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, and 191 user I/O pins, housed in a 240-pin RQFP (PowerQuad/FPQFP) package. It operates from a 5.0 V supply and delivers a 15 ns pin-to-pin propagation delay, making it a classic glue-logic and bus-interface solution for legacy 5 V systems.

A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the programmable logic hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, which makes it ideal for power-up sequencing, address decoding, and bus bridging. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using CMOS EEPROM technology, so the configuration is retained without an external boot device.

Key features include 560 macrocells organized into logic array blocks, 12,000 usable gates, 191 user I/O pins, in-system programmability (ISP) via the JTAG interface, and a maximum internal frequency of 145 MHz. The 15 ns pin-to-pin delay provides predictable, race-free timing that is essential for combinatorial address decoding and handshake logic in microprocessor systems.

The device uses 5.0 V CMOS technology with EEPROM-based configuration, giving it high noise immunity and direct compatibility with 5 V TTL/CMOS logic levels. Its 240-pin RQFP package with exposed pad supports surface mounting and provides 191 I/O for wide bus interfaces. The commercial temperature grade covers 0 C to 70 C.

Typical applications include legacy microprocessor glue logic, ISA/PCI bus interface logic, industrial control backplanes, telecom line-card control, test and measurement instrumentation, and FPGA companion logic. The EPM9560RC240-15 is widely used as a drop-in replacement in existing MAX 9000 designs and for sustaining long-lifecycle industrial and defense systems.

When designing with this device, note that it is a 5 V-only part and is not 3.3 V tolerant on all pins; level shifting is required when interfacing with modern low-voltage logic. Also confirm programming support, as MAX 9000 devices require a compatible JTAG programmer and the vendor's legacy programming software.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers evaluate the EPM9560RC240-15 for legacy and long-lifecycle designs.

Alternatif penggantian untuk EPM9560RC240-15 — paket yang sama, pin-pada-pin kompatibel. Bagian paket yang berbeda memerlukan kerja ulang PCB diabaikan.

Variasi di dalam seri ini

Model-series yang sama yang kompatibel dengan penggantian EPM9560RC240-15 (sama faktor bentuk dan footprint) — berbeda di dalam Package, RoHS Status, Family, Operating Temperature, Device Type.

Altera
Package: 240-pin RQFP (32x32 mm)
RoHS Status: RoHS non-compliant
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: 240-RQFP (32x32 mm, FQFP, Gull Wing)
Family: MAX 9000
Device Type: CPLD (Complex Programmable Logic Device)
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: 240-pin PowerQuad QFP (RQFP / EAR240)
Family: MAX 9000
Operating Temperature: 0C to +70C (commercial)
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: 240-pin RQFP (32x32 mm)
RoHS Status: Non-RoHS (legacy Altera part)
Family: MAX 9000
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: 240-pin RQFP (Plastic Quad Flatpack)
Family: MAX 9000
Operating Temperature: 0 C to +70 C (commercial)
Altera
Package: 240-pin RQFP (PowerQuad)
RoHS Status: ROHS3 Compliant
Family: MAX 9000
Bandingkan dengan EPM9560RC240-15 →
Intel
Package: 240-pin RQFP (Plastic Quad Flat Pack)
RoHS Status: ROHS3 Compliant (per fpgalink.com listing)
Family: MAX 9000
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: PQFP-240 (RC240) 0.500 mm pitch, gull-wing
Family: MAX 9000 (EPM9560)
Device Type: EE PLD / CPLD
Bandingkan dengan EPM9560RC240-15 →
Intel
Package: 240-pin RQFP (PowerQuad II)
Family: MAX 9000
Operating Temperature: 0C to +70C (Commercial)
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: RQFP-240 (240-pin Plastic Quad Flat Pack)
Family: MAX 9000 (third-generation Multiple Array MatriX)
Operating Temperature: 0C to +70C (Commercial)
Bandingkan dengan EPM9560RC240-15 →
Altera
Package: 240-pin RQFP (PowerQuad) with exposed pad
Family: MAX 9000
Operating Temperature: 0C to +70C (commercial)
Bandingkan dengan EPM9560RC240-15 →
Intel
RoHS Status: Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention)
Family: MAX 9000A
Operating Temperature: 0 C to +70 C (commercial)
Bandingkan dengan EPM9560RC240-15 →

EPM9560RC240-12

✅ Drop-In
Altera
📦 240-pin RQFP
MAX 9000 (EPM9560) · EE PLD / CPLD · 560 · 772 · 191 · 20 · 13.4 ns · -12 (13.4 ns tPD)

Kontak untuk harga

Lihat Datasheet →

EPM9560RC240-10

✅ Drop-In
Altera
📦 240-pin RQFP
Complex Programmable Logic Device (CPLD) · MAX 9000 · 12,000 gates · 560 · 12 · 144.9 MHz · 10 ns · 5 V

Kontak untuk harga

Lihat Datasheet →

EPM9560RC240-20

✅ Drop-In
Intel
📦 240-pin RQFP
MAX 9000 · MAX 9000 PLD Family · In System Programmable · 560 · 12,000 · 35 LABs · 191 · 20 ns

Kontak untuk harga

Lihat Datasheet →

EPM9560ARC240-10

✅ Drop-In
Altera
📦 240-pin RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · Multiple Array MatriX (MAX) - third generation · 12,000 · 560 · 191 (per Mouser listing) · 144.9 MHz · 11.4 ns

Kontak untuk harga

Lihat Datasheet →

EPM9560ARC240-10N

✅ Drop-In
Altera
📦 240-pin RQFP
MAX 9000 (CPLD) · CMOS EEPROM · 560 · 191 · 16 · 10 ns · 145 MHz · 5.0 V

Kontak untuk harga

Lihat Datasheet →

EPM9560RC240-15YY

✅ Drop-In
Intel
📦 240-pin RQFP
MAX 9000A · CMOS EEPROM-based CPLD · 560 · 12,000 · 191 · 117.6 MHz · 15 ns · 5.0 V

Kontak untuk harga

Lihat Datasheet →

EPM9560RC240-15 Rating Maksimal & Karakteristik Listrik

Logic Family MAX 9000 (CMOS EEPROM-based)
Macrocells 560
Usable Gates 12,000
User I/O Pins 191
Paket 240-pin RQFP (32x32 mm) with exposed pad
Pin-to-Pin Propagation Delay 15 ns
Maximum Internal Frequency 145 MHz
Tegangan Pemuat 5.0 V
Suhu Kerja 0 C to 70 C (commercial)
Tipe Mounting Surface Mount
Configuration Technology EEPROM (non-volatile)
In-System Programmability Yes (JTAG ISP)
Number of Terminals 240
Package Code FQFP / RQFP
Terminal Form Gull Wing
Package Shape Square

Konfigurasi Pin EPM9560RC240-15

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin produk 1 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
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Pin produk 214 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 215 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 216 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 217 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 218 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 219 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 220 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 221 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 222 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 223 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 224 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 225 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 226 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 227 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 228 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 229 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 230 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 231 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 232 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 233 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 234 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 235 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 236 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 237 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 238 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 239 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)
Pin produk 240 I/O — User I/O pin (per MAX 9000 240-RQFP pinout)

Aplikasi Umum

EPM9560RC240-15 cocok untuk 6 aplikasis: Legacy Microprocessor Glue Logic, ISA and PCI Bus Interface Logic, Industrial Control Backplane Logic, Telecom Line-Card Control, Test and Measurement Instrumentation, FPGA Companion and Configuration Logic.

🏭

Legacy Microprocessor Glue Logic

The EPM9560RC240-15 fits legacy microprocessor glue logic because its 15 ns pin-to-pin delay and 191 user I/O pins allow address decoding, chip-select generation, and wait-state logic to be implemented in a single 240-pin RQFP device. With 560 macrocells and 12,000 usable gates, it absorbs the discrete 74-series logic that surrounds 8-bit and 16-bit CPUs such as the 80C186 or 68000. The 5.0 V CMOS I/O interfaces directly with 5 V processor buses without level shifting, and the non-volatile EEPROM configuration means the logic is active immediately at power-up, before any processor boot code runs. A typical implementation places the CPLD between the CPU address/data bus and peripheral chip selects, adding roughly 15 ns to the decode path; designers must budget this delay against the processor's setup and hold requirements.

🖥️

ISA and PCI Bus Interface Logic

The EPM9560RC240-15 is used for ISA and PCI bus interface logic because its 191 I/O pins can bridge a wide 5 V backplane bus to local peripherals while its 15 ns propagation delay meets ISA timing with margin. The 560 macrocells implement bus transceivers, wait-state generators, and interrupt arbitration in one device, replacing dozens of discrete gates. Because the MAX 9000 architecture is EEPROM-based, the bus-interface personality is retained across power cycles, which is important for add-in cards that must enumerate deterministically. In a typical ISA card, the CPLD decodes address and control lines and drives the data bus through registered macrocells; the 15 ns delay must be subtracted from the bus cycle budget, and designers should register critical outputs to avoid race conditions on the shared backplane.

🏭

Industrial Control Backplane Logic

The EPM9560RC240-15 suits industrial control backplane logic because its 5.0 V CMOS inputs provide high noise immunity in electrically noisy factory environments, and its 560 macrocells can implement custom handshake, watchdog, and interlock logic. The 191 user I/O pins allow direct connection to backplane connectors without external multiplexing, and the non-volatile EEPROM configuration guarantees deterministic startup after brownouts or power cycling. A typical design uses the CPLD to sequence power rails, debounce limit switches, and generate strobes for motor-drive interfaces. The 15 ns pin-to-pin delay keeps control-loop latency low, but designers should note the commercial 0 C to 70 C temperature grade and provide adequate enclosure cooling or select an industrial-grade alternative for extended-temperature installations.

🌐

Telecom Line-Card Control

The EPM9560RC240-15 is used in telecom line-card control because its 191 I/O and 560 macrocells can implement time-slot assignment, alarm monitoring, and card-level status logic while the 145 MHz maximum internal frequency supports moderate-speed state machines. The 5.0 V CMOS interface matches legacy telecom backplanes, and EEPROM configuration ensures the card comes up in a known state without a configuration PROM. In a typical line card, the CPLD manages LED status, reads DIP switches, and arbitrates access to a shared control bus. The 15 ns pin-to-pin delay is adequate for control-plane timing but not for high-speed serial data paths, so the device is best used for housekeeping rather than payload processing. Verify thermal margin in sealed card cages.

🔧

Test and Measurement Instrumentation

The EPM9560RC240-15 fits test and measurement instrumentation because its deterministic 15 ns pin-to-pin delay and 560 macrocells allow precise trigger generation, counter/timer logic, and instrument bus interfacing in a single device. The 191 user I/O pins can drive front-panel controls and read back measurement status, while the non-volatile EEPROM configuration means the instrument is ready instantly at power-on, avoiding the boot latency of SRAM-based FPGAs. A typical implementation uses the CPLD to generate strobes for an ADC and to implement a state machine that sequences measurement cycles. Designers should register all outputs that cross clock domains and account for the 15 ns propagation delay in trigger-to-output timing budgets, especially in automated test equipment where jitter must be minimized.

🧩

FPGA Companion and Configuration Logic

The EPM9560RC240-15 serves as FPGA companion and configuration logic because its 560 macrocells can implement configuration sequencing, clock management, and board-level control for SRAM-based FPGAs, while its EEPROM non-volatility ensures the companion logic is alive before the FPGA is configured. The 191 I/O pins allow the CPLD to drive configuration mode pins, monitor DONE/INIT signals, and multiplex shared buses. In a typical board, the CPLD holds the FPGA in reset, applies the correct mode pins, and releases reset only after power rails are stable. The 15 ns delay is more than adequate for configuration handshaking, and the 5.0 V I/O can interface with legacy supervisory circuits. Designers should verify voltage compatibility if the FPGA uses 3.3 V or lower I/O banks.

What is the EPM9560RC240-15?
The EPM9560RC240-15 is an Intel (Altera) MAX 9000 family CPLD with 560 macrocells, 12,000 usable gates, and 191 user I/O pins in a 240-pin RQFP package. It operates from a 5.0 V supply with a 15 ns pin-to-pin propagation delay and 145 MHz maximum internal frequency, according to the Altera MAX 9000 datasheet.
What are the key specifications of EPM9560RC240-15 that engineers should know?
The EPM9560RC240-15 offers 560 macrocells, 12,000 usable gates, 191 user I/O pins, 15 ns pin-to-pin delay, 145 MHz maximum internal frequency, and 5.0 V operation in a 240-pin RQFP package. It uses non-volatile EEPROM configuration with JTAG in-system programmability, providing instant-on operation and deterministic timing for glue-logic and bus-interface designs.
What is the difference between EPM9560RC240-15 and EPM9560RC240-20?
The EPM9560RC240-15 has a 15 ns pin-to-pin propagation delay, while the EPM9560RC240-20 is a slower 20 ns speed grade. Both share the same 560-macrocell MAX 9000 die and 240-pin RQFP package, so the -15 can replace the -20 in most designs, but the -20 cannot always meet timing where the -15 is required.
What is the difference between EPM9560RC240-15 and EPM9560ARC240-10?
The EPM9560ARC240-10 is the enhanced MAX 9000A variant with a faster 10 ns pin-to-pin delay, while the EPM9560RC240-15 is the standard MAX 9000 at 15 ns. Both use the same 240-pin RQFP footprint and 560-macrocell architecture, but the ARC device offers higher performance and is often cited as a functional upgrade path.
What is the best drop-in replacement for EPM9560RC240-15?
The best drop-in replacement is the EPM9560RC240-12, which shares the same 240-pin RQFP package and 560-macrocell MAX 9000 architecture with a faster 12 ns delay. The EPM9560RC240-10 is also pin-compatible with a 10 ns delay. Both are same-family Intel/Altera parts that require no PCB changes.
Can EPM9560RC240-20 replace EPM9560RC240-15?
Yes, the EPM9560RC240-20 can physically replace the EPM9560RC240-15 because both use the identical 240-pin RQFP package and 560-macrocell MAX 9000 architecture. However, the -20 is a slower 20 ns speed grade, so timing margins must be re-verified; it is a safe drop-in only if the design has at least 5 ns of timing slack.
Where to buy EPM9560RC240-15 online?
The EPM9560RC240-15 is available through distributors such as DigiKey (part number 544-2366-ND), Mouser, and Octopart-listed suppliers. As of 2026-09-13, pricing starts around $218.40 per unit at quantity one. Because the part is obsolete, availability is limited to remaining distributor and broker stock, so verify stock before ordering.
What is the price of EPM9560RC240-15?
As of 2026-09-13, the EPM9560RC240-15 is priced at approximately $218.40 for quantity one, with volume discounts down to about $174.72 at 1,000 units. Pricing varies significantly between distributors and brokers because the device is obsolete, so obtain multiple quotes and confirm authenticity before purchase.
What is the lead time for EPM9560RC240-15?
Lead time for the EPM9560RC240-15 depends entirely on remaining distributor or broker inventory, since Intel/Altera has discontinued the MAX 9000 family. Typical broker lead times range from stock to several weeks. For long-lifecycle programs, secure buffer stock or qualify a pin-compatible alternative such as the EPM9560RC240-12.
Is EPM9560RC240-15 in stock?
Stock for the EPM9560RC240-15 fluctuates because the part is obsolete and no longer manufactured. Distributor listings such as DigiKey and Mouser show intermittent availability, and Octopart aggregates 23 distributors. Always confirm real-time stock and request a Certificate of Conformance, as counterfeit risk is elevated for obsolete CPLDs.
Where to download EPM9560RC240-15 datasheet PDF?
The EPM9560RC240-15 datasheet PDF is available from Alldatasheet (46-page MAX 9000 Programmable Logic Device Family document) and from distributor pages such as DigiKey and Datasheets.com. The datasheet covers the MAX 9000 architecture, pinouts, timing models, and JTAG programming details for the 240-pin RQFP package.
Where to find EPM9560RC240-15 pinout?
The EPM9560RC240-15 pinout is documented in the Altera MAX 9000 Programmable Logic Device Family datasheet, which lists all 240 RQFP pin assignments including 191 user I/O, dedicated clock inputs, VCCINT/VCCIO power pins, and JTAG TCK/TMS/TDI/TDO pins. Distributor product pages also link the same datasheet.
Is EPM9560RC240-15 suitable for industrial control applications?
Yes, the EPM9560RC240-15 is well suited to industrial control because its 5.0 V CMOS logic offers high noise immunity, its EEPROM configuration is instant-on and non-volatile, and its 15 ns deterministic delay suits address decoding and handshake logic. However, the commercial 0 C to 70 C grade may require an industrial-temperature alternative for harsh environments.
When should I choose EPM9560RC240-15 over EPM9560ARC240-10?
Choose the EPM9560RC240-15 when your design already meets timing at 15 ns and you want the lowest-cost or most readily available MAX 9000 option. Choose the EPM9560ARC240-10 when you need extra timing margin, higher performance, or a longer projected supply life, since the enhanced MAX 9000A variant is faster and often more available.
What is the best Intel equivalent for EPM9560RC240-15?
The best Intel/Altera equivalent is the EPM9560RC240-12, a same-family MAX 9000 CPLD with identical 560-macrocell architecture and 240-pin RQFP footprint but a faster 12 ns pin-to-pin delay. The EPM9560RC240-10 offers a further speed increase to 10 ns while remaining pin-compatible.

Data referensi engineering untuk EPM9560RC240-15 — pembandingan, panduan desain, dan informasi konformitas.

Panduan Pemilihan

Choose the EPM9560RC240-15 when your design already meets timing at 15 ns and you need a proven MAX 9000 CPLD with 560 macrocells and 191 I/O in a 240-pin RQFP package. If you need extra timing margin, select the EPM9560RC240-12 (12 ns) or EPM9560RC240-10 (10 ns), both pin-compatible drop-ins. For new designs or long-lifecycle programs, the EPM9560ARC240-10 enhanced MAX 9000A variant offers a 10 ns delay and often better availability. Avoid the EPM9560RC240-20 unless your design has at least 5 ns of timing slack, since its 20 ns delay is 25% slower. Because the MAX 9000 family is obsolete, secure buffer stock or qualify an alternative early, and always verify programming tool support before committing to production.

Pembandingan dengan Alternatif

Parameter Umum Produk Ini EPM9560RC240-12 EPM9560RC240-10 EPM9560RC240-20 EPM9560ARC240-10
Package 240-pin RQFP 240-pin RQFP - same 240-pin RQFP - same 240-pin RQFP - same 240-pin RQFP - same
Brand Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera)
Pin-to-Pin Delay 15 ns 12 ns 10 ns 20 ns 10 ns
Macrocells 560 560 560 560 560
Usable Gates 12,000 12,000 12,000 12,000 12,000
User I/O Pins 191 191 191 191 191
Supply Voltage 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V
Configuration Technology EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile)
Operating Temperature 0 C to 70 C (commercial) 0 C to 70 C (commercial) 0 C to 70 C (commercial) 0 C to 70 C (commercial) 0 C to 70 C (commercial)

Diferensiator Kunci

  • Faster speed grade available in the same footprint (vsEPM9560RC240-12)
  • Enhanced MAX 9000A upgrade path (vsEPM9560ARC240-10)
  • Lower-cost slower grade for non-critical logic (vsEPM9560RC240-20)

Catatan Desain

The EPM9560RC240-15 is a 5.0 V-only device and is not 3.3 V tolerant on all I/O pins. When interfacing with 3.3 V or lower logic, add level shifters or series resistors with clamping diodes. Decouple every VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 uF capacitor per power island. Estimated: with 191 I/O switching simultaneously at 5 V, transient current can exceed several hundred milliamps, so a low-impedance power plane is recommended.

The 240-pin RQFP package has a 0.5 mm lead pitch and an exposed thermal pad. Use a solder-mask-defined land pattern per the Altera MAX 9000 datasheet and reflow with a profile suitable for the package's MSL rating. Connect the exposed pad to a ground plane with a grid of thermal vias to spread heat. Estimated: at 5 V and typical ICC of a few hundred milliamps, the package can dissipate over 1 W, so the thermal pad is not optional.

MAX 9000 devices require a compatible JTAG programmer and legacy Altera programming software; modern toolchains may not support the family. Confirm programming support before committing to the design. Also verify that the 15 ns pin-to-pin delay is budgeted in all combinatorial paths, and register outputs that cross clock domains. Because the part is obsolete, qualify a pin-compatible alternative such as the EPM9560RC240-12 early to avoid supply disruption.

Informasi Konformitas

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Bebas Logam Lengket
Unknown
Bebas Halogena
Unknown
Mineral Konflik
Unknown

Compliance data not present in the provided verified web data. The EPM9560RC240-15 is a legacy commercial-grade CPLD; confirm RoHS/REACH status with the distributor or manufacturer before use in regulated markets.

Data disahkan pada: 2026-09-13 — data disahkan dan disusun oleh tim engineering komponen XAIPART

Pencarian Terkait

EPM9560RC240-15 EPM9560RC240-15 datasheet Intel EPM9560RC240-15 Altera MAX 9000 CPLD 560 macrocell 240-pin RQFP CPLD EPM9560RC240-15 industrial control EPM9560RC240-15 vs EPM9560RC240-20 EPM9560RC240-15 drop-in replacement EPM9560RC240-15 buy price what is the pin-to-pin delay of EPM9560RC240-15 EPM9560RC240-15 pinout RQFP obsolete CPLD replacement MAX 9000

Komponen dan Istilah Terkait

Intel Altera EPM9560RC240-15 EPM9560RC240-12 EPM9560RC240-10 EPM9560ARC240-10 MAX 9000 CPLD Complex Programmable Logic Device programmable logic device EEPROM JTAG in-system programmability 240-pin RQFP RQFP surface mount 5.0 V CMOS macrocell pin-to-pin propagation delay glue logic bus interface logic industrial control RoHS REACH
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