EPM9560RC240-15 - MAX 9000 CPLD 560 Macro Cells | Intel
MPN: EPM9560RC240-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $218.4 | $218.40 |
| 10 | $207.48 | $2,074.80 |
| 100 | $196.56 | $19,656.00 |
| 500 | $185.64 | $92,820.00 |
| 1,000 | $174.72 | $174,720.00 |
Drop-in alternatives for EPM9560RC240-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC240-12
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM9560RC240-10
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9560RC240-20
β Drop-Inβ In Stock
$122 / Unit
View Datasheet βEPM9560ARC240-10
β Drop-Inβ In Stock
$28.8 / Unit
View Datasheet βEPM9560ARC240-10N
β Drop-Inβ In Stock
$19.5 / Unit
View Datasheet βEPM9560RC240-15YY
β Drop-Inβ In Stock
$64.5 / Unit
View Datasheet βEPM9560RC240-15 Maximum Ratings & Electrical Characteristics
| Logic Family | MAX 9000 (CMOS EEPROM-based) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| User I/O Pins | 191 |
| Package | 240-pin RQFP (32x32 mm) with exposed pad |
| Pin-to-Pin Propagation Delay | 15 ns |
| Maximum Internal Frequency | 145 MHz |
| Supply Voltage | 5.0 V |
| Operating Temperature | 0 C to 70 C (commercial) |
| Mounting Type | Surface Mount |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG ISP) |
| Number of Terminals | 240 |
| Package Code | FQFP / RQFP |
| Terminal Form | Gull Wing |
| Package Shape | Square |
EPM9560RC240-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 2 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 3 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 4 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 5 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 6 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 7 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 8 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 9 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 10 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 11 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 15 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 20 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 60 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 61 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 80 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 89 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 90 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 92 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 99 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 100 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 101 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 102 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 119 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 120 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
| Pin 121 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 125 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 140 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 144 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 160 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 180 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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| Pin 191 | I/O β User I/O pin (per MAX 9000 240-RQFP pinout) |
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Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-15 is suitable for 6 applications: Legacy Microprocessor Glue Logic, ISA and PCI Bus Interface Logic, Industrial Control Backplane Logic, Telecom Line-Card Control, Test and Measurement Instrumentation, FPGA Companion and Configuration Logic.
Legacy Microprocessor Glue Logic
The EPM9560RC240-15 fits legacy microprocessor glue logic because its 15 ns pin-to-pin delay and 191 user I/O pins allow address decoding, chip-select generation, and wait-state logic to be implemented in a single 240-pin RQFP device. With 560 macrocells and 12,000 usable gates, it absorbs the discrete 74-series logic that surrounds 8-bit and 16-bit CPUs such as the 80C186 or 68000. The 5.0 V CMOS I/O interfaces directly with 5 V processor buses without level shifting, and the non-volatile EEPROM configuration means the logic is active immediately at power-up, before any processor boot code runs. A typical implementation places the CPLD between the CPU address/data bus and peripheral chip selects, adding roughly 15 ns to the decode path; designers must budget this delay against the processor's setup and hold requirements.
Recommended
ISA and PCI Bus Interface Logic
The EPM9560RC240-15 is used for ISA and PCI bus interface logic because its 191 I/O pins can bridge a wide 5 V backplane bus to local peripherals while its 15 ns propagation delay meets ISA timing with margin. The 560 macrocells implement bus transceivers, wait-state generators, and interrupt arbitration in one device, replacing dozens of discrete gates. Because the MAX 9000 architecture is EEPROM-based, the bus-interface personality is retained across power cycles, which is important for add-in cards that must enumerate deterministically. In a typical ISA card, the CPLD decodes address and control lines and drives the data bus through registered macrocells; the 15 ns delay must be subtracted from the bus cycle budget, and designers should register critical outputs to avoid race conditions on the shared backplane.
Recommended
Industrial Control Backplane Logic
The EPM9560RC240-15 suits industrial control backplane logic because its 5.0 V CMOS inputs provide high noise immunity in electrically noisy factory environments, and its 560 macrocells can implement custom handshake, watchdog, and interlock logic. The 191 user I/O pins allow direct connection to backplane connectors without external multiplexing, and the non-volatile EEPROM configuration guarantees deterministic startup after brownouts or power cycling. A typical design uses the CPLD to sequence power rails, debounce limit switches, and generate strobes for motor-drive interfaces. The 15 ns pin-to-pin delay keeps control-loop latency low, but designers should note the commercial 0 C to 70 C temperature grade and provide adequate enclosure cooling or select an industrial-grade alternative for extended-temperature installations.
Recommended
Telecom Line-Card Control
The EPM9560RC240-15 is used in telecom line-card control because its 191 I/O and 560 macrocells can implement time-slot assignment, alarm monitoring, and card-level status logic while the 145 MHz maximum internal frequency supports moderate-speed state machines. The 5.0 V CMOS interface matches legacy telecom backplanes, and EEPROM configuration ensures the card comes up in a known state without a configuration PROM. In a typical line card, the CPLD manages LED status, reads DIP switches, and arbitrates access to a shared control bus. The 15 ns pin-to-pin delay is adequate for control-plane timing but not for high-speed serial data paths, so the device is best used for housekeeping rather than payload processing. Verify thermal margin in sealed card cages.
Recommended
Test and Measurement Instrumentation
The EPM9560RC240-15 fits test and measurement instrumentation because its deterministic 15 ns pin-to-pin delay and 560 macrocells allow precise trigger generation, counter/timer logic, and instrument bus interfacing in a single device. The 191 user I/O pins can drive front-panel controls and read back measurement status, while the non-volatile EEPROM configuration means the instrument is ready instantly at power-on, avoiding the boot latency of SRAM-based FPGAs. A typical implementation uses the CPLD to generate strobes for an ADC and to implement a state machine that sequences measurement cycles. Designers should register all outputs that cross clock domains and account for the 15 ns propagation delay in trigger-to-output timing budgets, especially in automated test equipment where jitter must be minimized.
Recommended
FPGA Companion and Configuration Logic
The EPM9560RC240-15 serves as FPGA companion and configuration logic because its 560 macrocells can implement configuration sequencing, clock management, and board-level control for SRAM-based FPGAs, while its EEPROM non-volatility ensures the companion logic is alive before the FPGA is configured. The 191 I/O pins allow the CPLD to drive configuration mode pins, monitor DONE/INIT signals, and multiplex shared buses. In a typical board, the CPLD holds the FPGA in reset, applies the correct mode pins, and releases reset only after power rails are stable. The 15 ns delay is more than adequate for configuration handshaking, and the 5.0 V I/O can interface with legacy supervisory circuits. Designers should verify voltage compatibility if the FPGA uses 3.3 V or lower I/O banks.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-12 | EPM9560RC240-10 | EPM9560RC240-20 | EPM9560ARC240-10 |
|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Pin-to-Pin Delay | 15 ns | 12 ns | 10 ns | 20 ns | 10 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 191 | 191 | 191 | 191 | 191 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Max Internal Frequency | 145 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 100 MHz | [DATA_NEEDED] |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) |
Key Differentiators
- Faster speed grade available in the same footprint (vs EPM9560RC240-12)
- Enhanced MAX 9000A upgrade path (vs EPM9560ARC240-10)
- Lower-cost slower grade for non-critical logic (vs EPM9560RC240-20)
Design Notes
The EPM9560RC240-15 is a 5.0 V-only device and is not 3.3 V tolerant on all I/O pins. When interfacing with 3.3 V or lower logic, add level shifters or series resistors with clamping diodes. Decouple every VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 uF capacitor per power island. Estimated: with 191 I/O switching simultaneously at 5 V, transient current can exceed several hundred milliamps, so a low-impedance power plane is recommended.
The 240-pin RQFP package has a 0.5 mm lead pitch and an exposed thermal pad. Use a solder-mask-defined land pattern per the Altera MAX 9000 datasheet and reflow with a profile suitable for the package's MSL rating. Connect the exposed pad to a ground plane with a grid of thermal vias to spread heat. Estimated: at 5 V and typical ICC of a few hundred milliamps, the package can dissipate over 1 W, so the thermal pad is not optional.
MAX 9000 devices require a compatible JTAG programmer and legacy Altera programming software; modern toolchains may not support the family. Confirm programming support before committing to the design. Also verify that the 15 ns pin-to-pin delay is budgeted in all combinatorial paths, and register outputs that cross clock domains. Because the part is obsolete, qualify a pin-compatible alternative such as the EPM9560RC240-12 early to avoid supply disruption.
Compliance Information
Compliance data not present in the provided verified web data. The EPM9560RC240-15 is a legacy commercial-grade CPLD; confirm RoHS/REACH status with the distributor or manufacturer before use in regulated markets.
