FPGA & CPLD
製品 (6666)
XCZU47DR-1FFVE1156E - RFSoC, 930K Logic Cells | AMD
The AMD XCZU47DR-1FFVE1156E is a Zynq® UltraScale+™ RFSoC, a heterogeneous System-on-Chip (SoC) that integrates a Quad-core ARM® Cortex®-A53 MPCore™ application processor and a Dual-core ARM® Cortex™-R5 real-time processor with a substantial FPGA fabric. This device is housed in a 1156-FCBGA (35x35) package and is part of the Zynq UltraScale+ RFSoC family, designed for high-performance signal processing and wireless communications. A Zynq UltraScale+ RFSoC is a class of adaptive SoC that combines a multi-core ARM processing system (PS) with programmable logic (PL) and, in this 'DR' variant, integrated RF data converters. This integration eliminates the need for separate discrete data converters, reducing board space, power, and latency in RF systems. The architecture allows for a single-chip solution that can handle digital signal processing, control, and RF front-end tasks. Key features of the XCZU47DR-1FFVE1156E include 930K+ logic cells, a 500MHz maximum frequency for the FPGA fabric, and a 1.2GHz maximum frequency for the ARM Cortex-A53 processor. The device supports a wide range of I/O standards and includes features such as DMA and WDT. The operating temperature range is 0°C to 100°C (Tj), making it suitable for commercial and industrial environments. The RFSoC architecture integrates high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) directly into the device, enabling direct RF sampling and synthesis. This reduces the complexity of the analog front-end and improves system performance by eliminating the need for multiple intermediate frequency (IF) stages. The device also includes a comprehensive set of peripherals and interfaces for system integration. Typical applications for the XCZU47DR-1FFVE1156E include 5G wireless base stations, phased array radar, test and measurement equipment, and software-defined radio (SDR) systems. Its high logic density and integrated RF converters make it ideal for applications requiring high bandwidth and low latency. When designing with this device, careful attention must be paid to power supply decoupling and thermal management. The 1156-FCBGA package requires a robust PCB layout with adequate ground planes and thermal vias to ensure reliable operation at high power levels.
XCZU47DR-2FFVE1156I - RFSoC, 930K Logic Cells | AMD
The AMD XCZU47DR-2FFVE1156I is a Zynq UltraScale+ RFSoC, a heterogeneous System-on-Chip (SoC) that integrates a Quad-core ARM Cortex-A53 application processor, a Dual-core ARM Cortex-R5 real-time processor, and a large programmable logic (FPGA) fabric with over 930,000 logic cells. This device is housed in a 1156-pin FCBGA package (35x35 mm) and is designed for high-performance signal processing and wireless communications. A Zynq UltraScale+ RFSoC is a class of adaptive SoC that monolithically integrates data converters (ADCs and DACs) alongside the programmable logic and processing system, eliminating the need for separate converter chips in radio systems. This integration reduces board space, power, and latency, making it ideal for applications like 5G base stations, radar, and test equipment. Key features include the ARM Cortex-A53 application processor running at up to 1.333 GHz, the ARM Cortex-R5 real-time processor at up to 533 MHz, and the 930K+ logic cells for custom hardware acceleration. The device also supports high-speed transceivers and DDR4 memory interfaces, enabling high-throughput data movement. The -2 speed grade indicates a high-performance variant, and the I suffix denotes an industrial temperature grade (-40C to +100C). The RFSoC architecture combines the flexibility of FPGA fabric with the performance of dedicated converters, allowing designers to implement complex DSP chains in hardware while maintaining software programmability. The integrated converters support direct RF sampling, reducing analog front-end complexity. The device is supported by AMD's Vivado design suite and Vitis unified software platform. Typical applications include 5G NR base stations, phased array radar, software-defined radio, and medical imaging systems. The high logic cell count and processing power make it suitable for beamforming, channel estimation, and real-time signal analysis. The industrial temperature grade ensures reliable operation in harsh environments. When designing with this device, careful attention must be paid to power supply sequencing and decoupling, as the RFSoC has multiple power rails with specific requirements. The package pinout files from AMD (UG1075) should be consulted for accurate pin assignments.
XCZU4CG-1FBVB900E - Zynq UltraScale+ MPSoC CG | AMD
The AMD XCZU4CG-1FBVB900E is a Zynq UltraScale+ MPSoC CG device that integrates a dual-core ARM Cortex-A53 application processor and a dual-core ARM Cortex-R5 real-time processor with an UltraScale+ FPGA fabric. It comes in a 900-ball FCBGA package (31x31 mm) and is designed for high-performance embedded applications requiring both processing and programmable logic. A System-on-Chip (SoC) combines multiple components of a computer or electronic system into a single chip. The Zynq UltraScale+ MPSoC family specifically merges a multi-core ARM processing system (PS) with programmable logic (PL), enabling hardware-software co-design. This architecture allows designers to implement custom accelerators, high-speed I/O, and real-time control in the PL while running operating systems like Linux on the PS. Key features include 192K+ logic cells, 500 MHz PS clock, 1.2 GHz application processor clock, and support for DDR4, LPDDR4, and 32-bit/64-bit memory interfaces. The device also includes UltraScale+ programmable logic with 461K system logic cells, 21.1 Mb block RAM, and 1,152 DSP slices. It supports a wide range of I/O standards including LVCMOS, LVDS, and high-speed transceivers. The architecture combines the ARM Cortex-A53 application processor for high-level operating systems, the Cortex-R5 for real-time deterministic processing, and the FPGA fabric for custom logic. This heterogeneous computing platform enables efficient task partitioning, with the PS handling control and communication while the PL accelerates data-intensive algorithms. The device also features advanced security, power management, and system monitoring capabilities. Typical applications include software-defined radio, industrial automation, medical imaging, aerospace and defense systems, and data center acceleration. The combination of high-performance processing, programmable logic, and rich I/O makes it suitable for edge computing and embedded vision systems. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The 900-ball FCBGA package requires a multi-layer PCB with controlled impedance for high-speed signals. AMD provides reference designs and power management solutions to simplify the design process.
XCZU4EV-1SFVC784E - Zynq UltraScale+ MPSoC EV | AMD
The AMD XCZU4EV-1SFVC784E is a Zynq® UltraScale+™ MPSoC EV device that integrates a quad-core ARM® Cortex®-A53 MPCore™ application processor, a dual-core ARM® Cortex™-R5 real-time processor, and an ARM Mali™-400 MP2 graphics processing unit into a single System-on-Chip (SoC). This device is housed in a 784-pin FCBGA package (23x23 mm) and is designed for high-performance embedded applications requiring both processing and programmable logic. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines a multi-core ARM processing system (PS) with programmable logic (PL) fabric on a single die. This architecture enables designers to implement custom hardware accelerators, high-speed I/O interfaces, and complex signal processing chains in the PL while running operating systems and application software on the PS. The EV variant specifically adds a video codec unit (VCU) for hardware-accelerated video encoding and decoding. The XCZU4EV-1SFVC784E features 192K+ logic cells in the programmable logic fabric, providing substantial capacity for custom logic designs. The processing system operates at speeds up to 1.2 GHz for the Cortex-A53 cores, 600 MHz for the Cortex-R5 cores, and 500 MHz for the Mali-400 GPU. This combination of processing power and programmable logic makes it suitable for a wide range of applications. Key features include support for DDR4 memory interfaces, high-speed transceivers, and a comprehensive set of I/O standards. The device supports multiple boot modes including Quad-SPI flash, SD card, and JTAG. The 784-pin FCBGA package provides excellent thermal and electrical performance for high-speed designs. Typical applications include video processing systems, software-defined radio, industrial automation, medical imaging, and aerospace/defense systems. The device's ability to handle both real-time processing and complex algorithms makes it ideal for edge computing and embedded vision applications. When designing with this device, careful attention must be paid to power supply sequencing, clocking architecture, and thermal management. The device requires multiple power rails with specific voltage levels and sequencing requirements as detailed in the power management documentation.
XCZU4EV-2SFVC784I - Zynq UltraScale+ MPSoC EV | AMD
The AMD XCZU4EV-2SFVC784I is a Zynq UltraScale+ MPSoC EV device that integrates a quad-core ARM Cortex-A53 application processor, a dual-core ARM Cortex-R5 real-time processor, and an ARM Mali-400 MP2 graphics processing unit with programmable logic. This System-on-Chip (SoC) combines the flexibility of an FPGA with the performance of a multi-core processing system, making it suitable for a wide range of embedded applications. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that merges a processing system (PS) with programmable logic (PL) on a single die. The PS contains the ARM cores, memory interfaces, and peripheral controllers, while the PL provides reconfigurable hardware acceleration. This architecture allows designers to implement complex algorithms in hardware for high performance and low latency, while the software-defined PS handles system-level tasks and connectivity. Key features of the XCZU4EV-2SFVC784I include 192K+ logic cells, 533MHz for the Cortex-R5, 600MHz for the Mali-400 MP2, and 1.3GHz for the Cortex-A53. The device is housed in a 784-FCBGA package measuring 23x23 mm, offering 252 user I/O pins. This combination of processing power and programmable logic makes it ideal for applications requiring both high-level operating systems and real-time, low-latency control. The XCZU4EV-2SFVC784I is built on a 16nm process technology, providing a balance of performance and power efficiency. The device supports a wide range of I/O standards and includes high-speed transceivers for serial communication. The integrated memory controllers support DDR4, LPDDR4, and other memory types, enabling high-bandwidth data processing. Typical applications include software-defined radio, video processing, industrial automation, and aerospace and defense systems. The combination of ARM cores and FPGA fabric allows for flexible, high-performance solutions that can be adapted to changing requirements. When designing with this device, careful attention must be paid to power supply sequencing, clocking, and thermal management. The 784-FCBGA package requires a multi-layer PCB with adequate decoupling and thermal vias to ensure reliable operation at high clock speeds.
XCZU5CG-1SFVC784E - Zynq UltraScale+ MPSoC, 256K Logic Cells | AMD
The AMD (Xilinx) XCZU5CG-1SFVC784E is a Zynq UltraScale+ MPSoC integrating a programmable logic fabric with a heterogeneous multiprocessing system on a single die, housed in a 784-ball FCBGA package measuring 23x23 mm. The CG (Cost-Grade) variant supplies 256K+ system logic cells with the dual-core ARM Cortex-R5 real-time processor, dual-core ARM Cortex-A53 application processor subsystem with CoreSight debug, and the Mali-400 MP2 GPU. The part operates across 500 MHz fabric / 1.2 GHz PS clock domains and supports a 0.85 V core supply built on a 20 nm process node. A Multi-Processor System-on-Chip (MPSoC) merges hardened ARM cores with programmable FPGA logic, enabling designers to partition deterministic control tasks to the Cortex-R5, high-level application code to the Cortex-A53 running Linux, and custom accelerators into the FPGA fabric. Within the broader taxonomy, the Zynq UltraScale+ MPSoC sits above single-core Cortex-M microcontrollers and below discrete CPU+FPGA board-level designs, providing hardware/software co-design in one silicon device. Architecturally the CG family omits the video codec unit (VCU) and the high-end Programmable Logic density of the EG/EV variants, but retains the same Memory Protection Unit (XMPU) and DDR4 controller infrastructure. Designers benefit from the integrated GTH/GTY transceivers, AXI4 high-performance interconnects, and tight PS-PL coupling without external bridges. Typical applications include industrial machine vision, motor control drives, edge AI inference gateways, software-defined radio front-ends, and automotive driver-assistance ECUs where deterministic response and Linux-class processing coexist on one die. Designers should validate DDR4 routing against the Zynq UltraScale+ PCB guidelines (UG1075) and ensure the heat spreader/FCLGA lid is properly attached with a thermal interface material, since the 784-FCBGA package relies on top-side cooling for sustained workloads.
XCZU5EV-1SFVC784E - Zynq UltraScale+ MPSoC EV | AMD
The AMD XCZU5EV-1SFVC784E is a Zynq® UltraScale+™ MPSoC EV device that integrates a quad-core ARM® Cortex®-A53 application processor, a dual-core ARM® Cortex™-R5 real-time processor, and an ARM Mali™-400 MP2 graphics processing unit with programmable logic. This System-on-Chip (SoC) is housed in a 784-pin FCBGA package (23x23 mm) and is designed for high-performance embedded applications requiring both processing and hardware acceleration. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines a multi-core ARM processing system (PS) with FPGA programmable logic (PL) on a single die. This architecture allows designers to implement complex algorithms in hardware for performance and power efficiency while maintaining the flexibility of software-defined control. The EV family specifically adds video codec units, making it ideal for multimedia and vision applications. Key features of the XCZU5EV-1SFVC784E include 256K+ logic cells, a 500MHz Cortex-A53 processor, a 600MHz Cortex-R5 processor, and a 1.2GHz Mali-400 MP2 GPU. The device supports high-speed transceivers and a wide range of I/O standards, enabling high-bandwidth data movement. The programmable logic is based on the UltraScale+ architecture, offering advanced clocking, DSP slices, and block RAM resources. Technically, the XCZU5EV-1SFVC784E is fabricated on a 16nm process, providing a balance of performance and power. The PS and PL are connected via a high-bandwidth AXI interconnect, allowing low-latency communication. The device includes security features such as AES and RSA for secure boot, and supports a comprehensive set of peripherals including USB, PCIe, and Ethernet. Typical applications include software-defined radio, machine vision, medical imaging, and aerospace/defense systems. The combination of ARM cores and FPGA fabric makes it suitable for edge computing where low latency and high throughput are critical. The Mali-400 GPU enables graphical user interfaces and video processing. When designing with this device, careful attention must be paid to power supply sequencing and decoupling. The multiple power rails (VCCINT, VCCAUX, VCCO) require proper filtering and sequencing to ensure reliable operation. The FCBGA package requires a multi-layer PCB with controlled impedance for high-speed signals.
XCZU5EV-2SFVC784I - Zynq UltraScale+ MPSoC EV | AMD
The AMD XCZU5EV-2SFVC784I is a Zynq® UltraScale+™ MPSoC EV device that integrates a quad-core ARM® Cortex®-A53 MPCore™ application processor, a dual-core ARM® Cortex™-R5 real-time processor, and an ARM Mali™-400 MP2 graphics processing unit with programmable logic. This System-on-Chip (SoC) is housed in a 784-pin FCBGA package (23x23 mm) and is designed for high-performance embedded applications requiring both processing and hardware acceleration. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines a multi-core ARM-based processing system (PS) with FPGA programmable logic (PL) on a single die. This architecture allows designers to implement complex algorithms in hardware for high throughput and low latency, while the PS handles operating systems and control tasks. The EV family specifically adds video codec units, making it ideal for multimedia and vision applications. Key features of the XCZU5EV-2SFVC784I include 256K+ logic cells, a maximum operating frequency of 1.3 GHz for the Cortex-A53 cores, 600 MHz for the Cortex-R5 cores, and 533 MHz for the Mali-400 GPU. The device supports a wide range of I/O standards and includes high-speed transceivers for serial communication. The -2 speed grade indicates a balanced performance-power profile. The device is built on TSMC's 16nm FinFET process technology, offering a good balance of performance and power efficiency. The programmable logic is based on the UltraScale+ architecture, featuring 6-input look-up tables (LUTs), block RAM, and DSP slices. The integrated video codec supports H.264/H.265 encoding and decoding, offloading these tasks from the CPU. Typical applications include video surveillance systems, medical imaging equipment, automotive driver assistance systems, and software-defined radio. The combination of ARM processing, FPGA flexibility, and video codec support makes it a versatile platform for edge computing and vision-based AI. When designing with this device, careful attention must be paid to power supply sequencing and decoupling. The multiple power rails (VCCINT, VCCAUX, VCCO, etc.) require proper filtering and sequencing to ensure reliable operation. The FCBGA package requires a multi-layer PCB with controlled impedance traces for high-speed signals.
XCZU6CG-1FFVC900E - Zynq UltraScale+ MPSoC CG, Dual A53/R5, 900-FCBGA | AMD
The AMD (formerly Xilinx) XCZU6CG-1FFVC900E is a heterogeneous Zynq UltraScale+ MPSoC CG device integrating a dual-core ARM Cortex-A53 application processor (up to 1.2 GHz) with a dual-core ARM Cortex-R5 real-time processor (up to 500 MHz), CoreSight debug, and approximately 469K+ programmable logic cells, all housed in a 900-ball FCBGA (31x31 mm) package. The CG subfamily is the cost-optimized dual-core variant without the integrated H.264/H.265 video codec, which AMD explicitly targets at industrial motor control and sensor-fusion workloads. The -1 speed grade and E (0C to +100C) extended temperature grade make this part well suited for industrial and edge deployments where power-constrained enclosures and harsh environments are common. A heterogeneous MPSoC (Multiprocessor System-on-Chip) is a class of integrated device that tightly couples deterministic real-time microcontrollers, application-class CPUs, graphics/video engines, and hardware-programmable FPGA fabric on a single die. The Zynq UltraScale+ family sits at the top of AMD's SoC taxonomy: heterogeneous MPSoC > Zynq UltraScale+ > Zynq-7000 > earlier Zynq devices, and competes directly with Microchip PolarFire SoC, NXP Layerscape, and TI Jacinto in the embedded edge AI and industrial control segment. Key features include dual ARM Cortex-A53 cores with NEON/SIMD and ARMv8-A 64-bit support, dual ARM Cortex-R5 cores with lock-step capability, ARM Mali-400MP2 GPU, integrated memory controller supporting DDR4/LPDDR4 with ECC, high-speed transceivers (GTH/GTX), common-use peripherals such as USB 2.0, Gigabit Ethernet, CAN, SPI, I2C, UART, and 256-bit AES/RSA hardware root of trust for secure boot. The 900-FCBGA package exposes approximately 256 user I/O pins grouped into high-range, high-performance, and high-density banks. The programmable logic portion contains roughly 469K system logic cells plus DSP slices, block RAM, and UltraRAM, all accessible through the ARM PS-PL AXI interconnect. Designers can implement custom peripherals, hardware accelerators, and vision pipelines in the PL fabric, while the hardened PS handles real-time and application tasks. The Vivado and Vitis toolchains from AMD provide C/C++, RTL, and high-level synthesis flows. Typical applications include industrial motor drives, robotics, sensor fusion gateways, machine-vision controllers, 5G edge radio units, automotive ADAS prototyping, and medical imaging. The CG subfamily is optimal when video encode/decode is not needed but deterministic real-time control, Linux application processing, and FPGA acceleration are all required. When designing with this device, allocate PCB power-delivery for the multi-rail requirement (typically 0.85 V VCCINT, 1.8 V VCCAUX, 0.9 V DDR4 VTT, plus 3.3 V I/O). Proper decoupling, ground plane stitching under the BGA, and length-matched DDR4 address/command traces are critical; AMD UG583 and UG1075 are the primary hardware-design references. This page synthesizes distributor pricing, validated drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
XCZU7CG-L2FFVF1517E - Zynq UltraScale+ MPSoC CG | AMD
The AMD XCZU7CG-L2FFVF1517E is a Zynq UltraScale+ MPSoC CG device that integrates a dual-core ARM Cortex-A53 application processor and a dual-core ARM Cortex-R5 real-time processor with an UltraScale+ programmable logic fabric. This System-on-Chip (SoC) is housed in a 1517-ball FCBGA package (40x40 mm) and is designed for high-performance embedded applications requiring both processing and hardware acceleration. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines multi-core ARM processors with FPGA fabric on a single die. The CG variant is the cost-optimized family, offering a balanced mix of processing system (PS) and programmable logic (PL) resources. The device supports a wide range of operating systems including Linux, VxWorks, and bare-metal applications, making it a versatile choice for edge computing, industrial automation, and aerospace systems. Key features of the XCZU7CG-L2FFVF1517E include 504K+ logic cells, 533 MHz maximum frequency for the Cortex-A53 cores, and 1.3 GHz for the Cortex-R5 cores. The device also includes 256 KB of on-chip memory, high-speed transceivers, and a comprehensive set of I/O interfaces. The 'L2' speed grade indicates a high-performance variant, and the 'E' suffix denotes an extended temperature range (-40°C to +100°C). From an architectural perspective, the XCZU7CG integrates a quad-core ARM Cortex-A53 MPCore with CoreSight debug, a dual-core ARM Cortex-R5 with CoreSight, and a Mali-400 MP2 GPU. The programmable logic is based on the UltraScale+ architecture, featuring 6-input LUTs, block RAM, and DSP slices. The device supports PCIe Gen3, USB 3.0, DisplayPort, and Gigabit Ethernet, providing extensive connectivity options. Typical applications include software-defined radio, machine vision, autonomous driving, and data center acceleration. The combination of high-performance processing and reconfigurable logic allows designers to implement complex algorithms with low latency and high throughput. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The FCBGA package requires a multi-layer PCB with controlled impedance for high-speed signals. AMD provides comprehensive reference designs and documentation to facilitate development.
XCZU7EV-1FFVC1156E - Zynq UltraScale+ MPSoC EV | AMD
The AMD XCZU7EV-1FFVC1156E is a Zynq UltraScale+ MPSoC EV device that integrates a quad-core ARM Cortex-A53 application processor, dual-core ARM Cortex-R5 real-time processor, and ARM Mali-400 MP2 graphics processing unit with programmable logic. It is housed in a 1156-ball FCBGA package (35x35 mm) and operates with a core voltage of 0.85V. The device features 504K+ logic cells and supports speeds of 500MHz, 600MHz, and 1.2GHz for the respective processor subsystems. A Zynq UltraScale+ MPSoC is a multiprocessor system-on-chip that combines a hardened processing system (PS) with programmable logic (PL) on a single device. This architecture enables designers to implement complex embedded systems with both software flexibility and hardware acceleration. The EV variant specifically targets video codec applications, providing hardware-accelerated H.264/H.265 encoding and decoding capabilities. Key features of the XCZU7EV-1FFVC1156E include the 504K+ logic cells for extensive programmable logic, the quad-core A53 application processor for high-performance computing, and the Mali-400 MP2 GPU for graphics acceleration. The device also supports a wide range of high-speed serial transceivers and memory interfaces, making it suitable for demanding applications. The device is built on TSMC's 16nm process technology, offering a balance of performance and power efficiency. The programmable logic is based on the UltraScale+ architecture, which provides advanced features such as integrated block RAM, DSP slices, and high-speed transceivers. The processing system includes a comprehensive set of peripherals, including USB, PCIe, and Ethernet controllers. Typical applications for the XCZU7EV-1FFVC1156E include video processing and surveillance systems, 5G wireless infrastructure, industrial automation, and automotive ADAS. The combination of high-performance processing and programmable logic makes it ideal for applications requiring both software flexibility and hardware acceleration. When designing with this device, careful attention must be paid to power supply sequencing and decoupling. The multiple power rails (VCCINT, VCCAUX, VCCO, etc.) require proper sequencing to ensure reliable operation. Additionally, the high-speed transceivers require careful PCB layout to maintain signal integrity.
XCZU7EV-2FFVC1156I - Zynq UltraScale+ MPSoC EV, 504K Logic Cells | AMD
The AMD XCZU7EV-2FFVC1156I is a Zynq UltraScale+ MPSoC EV device that integrates a quad-core ARM Cortex-A53 application processor, a dual-core ARM Cortex-R5 real-time processor, and an ARM Mali-400 MP2 graphics processing unit with a programmable FPGA fabric. This System-on-Chip (SoC) is housed in a 1156-ball FCBGA package measuring 35x35 mm and operates with a maximum clock frequency of 1.3 GHz for the Cortex-A53 cores, 600 MHz for the Cortex-R5 cores, and 533 MHz for the FPGA fabric. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines a multi-core ARM processing system (PS) with programmable logic (PL) on a single device. This architecture enables designers to implement complex algorithms in hardware for high throughput while maintaining the flexibility of software-based control. The EV variant specifically targets video codec applications, providing hardware-accelerated H.264/H.265 encode and decode capabilities that offload the processing system. Key features of the XCZU7EV-2FFVC1156I include 504K+ logic cells, 34.9 Mb of block RAM, and 1,152 DSP slices in the programmable logic. The device supports a wide range of I/O standards including LVCMOS, LVDS, and high-speed transceivers. The -2 speed grade offers a balanced performance-power trade-off, making it suitable for a variety of embedded applications. The processing system includes a memory management unit, cache coherence, and a rich set of peripherals such as USB 3.0, DisplayPort, SATA, and PCIe. The device also features advanced security with AES and RSA decryption, and supports secure boot. The integration of these capabilities reduces system complexity and bill-of-materials cost. Typical applications include video surveillance systems, medical imaging equipment, software-defined radio, and automotive driver assistance systems. The combination of high-performance processing and programmable logic makes it ideal for edge computing and AI inference workloads. When designing with this device, careful attention must be paid to power supply sequencing and decoupling. The multiple power rails require a controlled power-up sequence to prevent latch-up or damage. A dedicated power management IC is recommended to ensure reliable operation.
XCZU9CG-L2FFVB1156E - Zynq UltraScale+ MPSoC CG, 599K+ Logic Cells | AMD
The AMD (formerly Xilinx) XCZU9CG-L2FFVB1156E is a Zynq UltraScale+ MPSoC in the CG (Cost-Optimized) family, integrating a Dual-core ARM Cortex-A53 MPCore application processor with CoreSight, a Dual-core ARM Cortex-R5 real-time processor with CoreSight, and 599K+ UltraScale+ FPGA logic cells in a single 1156-ball FCBGA (35x35 mm) package. The part operates at -2 (extended) speed grade and is offered as an E (engineering sample / standard) temperature grade device, supporting the heterogeneous compute requirements of advanced embedded systems. A Zynq UltraScale+ MPSoC (Multiprocessor System-on-Chip) is a class of adaptive SoC devices that tightly couples an FPGA fabric with multi-core ARM CPUs, GPU, and real-time controllers on a single die. Within AMD's portfolio, Zynq UltraScale+ devices sit at the top of the MPSoC hierarchy under the Adaptive Compute Acceleration Platform (ACAP) family, preceding Versal devices; the CG sub-family omits the Mali GPU and Video Codec Unit to reduce silicon cost while retaining the A53 + R5 + FPGA triad - a popular middle-ground for compute-intensive embedded designs that do not require on-chip graphics. Key features of the XCZU9CG-L2FFVB1156E include up to 599K logic cells, an extensive DDR4/LPDDR4 memory controller subsystem, integrated Programmable Logic (PL) hardening blocks (DSP48E2, UltraRAM, BRAM), and rich connectivity with high-speed transceivers (GTH), PCIe Gen2/3, SATA, DisplayPort, and USB 3.0 controllers. The device is built on TSMC's 16nm FinFET process and supports MultiBoot, partial reconfiguration, and platform management via PMU + CSU. The 1156-ball FCBGA package offers a 35x35 mm body compatible with the ZU7CG / ZU9EG / ZU15EG stack, enabling footprint-scalable design. The architecture integrates high-speed serial interfaces directly into the PL through GTH transceivers supporting up to 16.3 Gb/s line rates. Security features include ARM TrustZone, secure boot, hardware root of trust, and AES/SHA acceleration engines. The embedded programmers' view exposes four ARM cores through separate SMP/AMP clusters, allowing Linux-and-RTOS concurrent operation with deterministic real-time response. Typical applications include industrial machine vision, 5G baseband preprocessing, ADAS sensor fusion, medical imaging, and military/aerospace signal processing. The CG sub-family cost-down makes the device attractive when the Mali GPU is not needed but ARM Cortex-A53 + FPGA horsepower is still required. Designers also use the ZU9CG in IoT edge gateways, software-defined radio front-ends, and broadcast video processing at 4K/8K resolutions. When designing with the XCZU9CG-L2FFVB1156E, ensure that the selected reference design accommodates the FCBGA-1156 footprint thermal requirements - the package does not expose a thermal pad in the conventional sense but requires 4-8 stacked PCB layers with microvia stitching for signal and ground integrity. Power sequencing of MIO banks and PS/PL voltage rails must follow UG1085 / UG1087 (Zynq UltraScale+ PCB Design Guide); designers usually employ a UCD90120A or equivalent sequencer. The device must be paired with an AMD-supported JTAG programmer (Xilinx Platform Cable USB II or SmartLynq+). This page synthesizes distributor availability, drop-in same-family and same-package alternatives, and practical design notes not consolidated into a single document on the AMD datasheet site.
XCZU9EG-1FFVB1156E - Zynq UltraScale+ MPSoC EG | AMD
The AMD XCZU9EG-1FFVB1156E is a Zynq UltraScale+ MPSoC EG family system-on-chip (SoC) that integrates a quad-core ARM Cortex-A53 application processor, a dual-core ARM Cortex-R5 real-time processor, and an ARM Mali-400 MP2 graphics processing unit with programmable logic. It is housed in a 1156-ball FCBGA package (35x35 mm) and is designed for high-performance embedded applications requiring both processing and hardware acceleration. A Zynq UltraScale+ MPSoC is a heterogeneous computing platform that combines a multi-core ARM-based processing system (PS) with Xilinx programmable logic (PL) on a single device. The EG variant is optimized for embedded and industrial applications, offering a balance of processing power, logic density, and I/O capabilities. This architecture enables designers to implement complex algorithms in hardware while maintaining software flexibility. Key features include 599,550 logic cells, 32.1 Mb of block RAM, and 2,520 DSP slices in the programmable logic. The processing system operates at speeds up to 1.2 GHz for the Cortex-A53, 600 MHz for the Cortex-R5, and 500 MHz for the Mali-400 GPU. The device supports a wide range of high-speed transceivers and I/O standards, making it suitable for diverse interface requirements. The XCZU9EG-1FFVB1156E is fabricated on a 16nm process technology, providing high performance with low power consumption. The device includes comprehensive security features such as AES decryption, RSA authentication, and secure boot. It also supports partial reconfiguration, allowing dynamic updates to the programmable logic without interrupting system operation. Typical applications include software-defined radio, medical imaging, industrial automation, and aerospace and defense systems. The combination of ARM processing and FPGA fabric makes it ideal for edge computing, machine vision, and 5G infrastructure where low latency and high throughput are critical. When designing with this device, careful attention must be paid to power supply sequencing and decoupling. The multiple power rails require proper filtering and sequencing to ensure reliable operation. Thermal management is also critical due to the high power dissipation of the device under full load.
XCZU9EG-2FFVB1156I - Zynq UltraScale+ MPSoC EG | AMD
The AMD XCZU9EG-2FFVB1156I is a Zynq UltraScale+ MPSoC EG family device, combining a quad-core ARM Cortex-A53 application processor, dual-core ARM Cortex-R5 real-time processor, ARM Mali-400 MP2 graphics processing unit, and 599,550 programmable logic cells in a single 1156-pin FCBGA package. This System-on-Chip (SoC) integrates the processing system (PS) and programmable logic (PL) on one die, enabling heterogeneous computing for demanding embedded applications. A Zynq UltraScale+ MPSoC is a class of adaptive SoC that pairs multi-core ARM processing with FPGA fabric. The EG variant targets embedded and industrial applications, offering a balance of processing performance, programmable logic capacity, and I/O flexibility. It sits within the broader hierarchy: Zynq UltraScale+ MPSoC -> adaptive SoC -> System-on-Chip -> semiconductor device. Key features include 599,550 logic cells, 32.1 Mb of block RAM, 1,968 DSP slices, and support for 533 MHz (Cortex-R5), 600 MHz (Mali-400), and 1.3 GHz (Cortex-A53) clock speeds. The device operates at 0.85V core voltage and is fabricated on a 20nm process. The -2 speed grade offers a balance of performance and power efficiency. The architecture integrates the PS with the PL via high-bandwidth AXI interfaces, enabling low-latency data movement between software and hardware accelerators. The Mali-400 MP2 GPU supports 2D/3D graphics, while the video codec unit handles H.264/H.265 encoding and decoding. The device includes comprehensive security features such as RSA authentication, AES decryption, and secure boot. Typical applications include software-defined radio, industrial motor control, medical imaging, aerospace and defense systems, and multi-axis robotics. The combination of real-time processing (Cortex-R5), application processing (Cortex-A53), and programmable logic makes it suitable for complex control and signal processing tasks. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The 1156-pin FCBGA package requires a multi-layer PCB with controlled impedance for high-speed transceivers and DDR memory interfaces.
XCZU9EG-2FFVC900E - Zynq UltraScale+ MPSoC EG | AMD
The AMD XCZU9EG-2FFVC900E is a Zynq UltraScale+ MPSoC EG family device, integrating a quad-core ARM Cortex-A53 application processor, dual-core ARM Cortex-R5 real-time processor, and ARM Mali-400 MP2 graphics processing unit with programmable logic. It is housed in a 900-ball FCBGA package (31x31 mm) and is designed for high-performance embedded applications requiring both processing and FPGA flexibility. A System-on-Chip (SoC) FPGA combines a hard processor system (PS) with programmable logic (PL) on a single die, enabling software and hardware co-design. The Zynq UltraScale+ MPSoC family extends this concept with heterogeneous processing, including real-time and graphics cores, making it suitable for advanced driver assistance systems (ADAS), industrial automation, and aerospace applications. Key features include 599K+ logic cells, 533 MHz for the Cortex-A53, 600 MHz for the Cortex-R5, and 1.3 GHz for the Mali-400 MP2. The device supports DDR4, LPDDR4, and 32-bit/64-bit memory interfaces, and includes high-speed transceivers for serial connectivity. The EG variant provides a balanced mix of logic and DSP resources, with 2,520 DSP slices and 32.1 Mb of block RAM. The architecture leverages TSMC 16nm FinFET process technology, offering high performance with low power consumption. The programmable logic is based on the UltraScale+ architecture, featuring enhanced routing, clocking, and I/O capabilities. The device supports partial reconfiguration, enabling dynamic updates to the PL while the PS continues operation. Typical applications include 5G wireless baseband processing, machine vision systems, medical imaging, and defense electronics. The combination of ARM cores and FPGA fabric allows for real-time signal processing, hardware acceleration, and flexible I/O interfacing. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The 900-ball FCBGA package requires a multi-layer PCB with controlled impedance for high-speed signals. AMD provides comprehensive design resources, including the Zynq UltraScale+ MPSoC data sheet (DS891) and pinout files.
iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi
The Lattice Semiconductor iCE40LP384-SG48 is an ultra-low-power Field Programmable Gate Array (FPGA) from the iCE40 LP family, delivering 384 Look-Up Tables (LUTs) in a 48-pin QFN (SG48) package with 1.2V core voltage and 21 user I/O. It is fabricated on a 40 nm CMOS process optimized for minimal static and dynamic power consumption, targeting mobile, handheld, and energy-harvesting designs where battery life dominates the bill of materials. The device integrates a hardened I2C core, SPI configuration interface, and on-chip PLL blocks, providing a complete glue-logic platform in a sub-1 mW active power envelope. An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (LUTs), programmable interconnect, and I/O cells that can be re-programmed to implement arbitrary digital logic. Low-power FPGAs such as the iCE40 LP family occupy a unique tier in the programmable logic hierarchy - sitting above fixed-function ASICs (which offer zero flexibility) and below high-density FPGAs from Xilinx and Intel (which offer millions of LUTs at the cost of watts). The iCE40 LP family is the de-facto choice when an application needs custom logic, multiple interfaces, or hardware acceleration, but the system can only afford a few hundred microwatts of quiescent draw. Within the Lattice portfolio, iCE40LP sits between the older iCE65 and the higher-density ECP5 family. Key features include 384 4-input LUTs, 21 user I/O pins, embedded RAM (4 kbits block RAM equivalent), two 16-bit timers/counters, two I2C controllers, one SPI controller, and a hard PLL supporting clock multiplication. The device operates from a 1.14 V to 1.26 V core supply with separate I/O bank supplies from 1.71 V to 3.465 V, enabling direct interfacing to 1.8 V, 2.5 V, and 3.3 V peripherals. Typical static current is below 100 uA at 25 C, and active current scales linearly with toggle rate and logic utilization. Architecturally, the iCE40LP384 uses a non-volatile SRAM configuration cell (volatile SRAM, but loaded from NV memory at boot) backed by NVCM or SPI Flash. Logic is implemented as 4-input LUTs feeding a programmable interconnect fabric, with carry chains for arithmetic and block RAM for storage. The hard I2C and SPI controllers reduce LUT usage for common bus interfaces, leaving more logic free for application-specific state machines and datapaths. Typical applications include mobile device glue logic, IoT sensor hubs, wearable sensor aggregation, low-power display controllers (SPI/parallel LCD), handheld medical peripherals, and battery-powered industrial sensor nodes. The 48-pin QFN package balances I/O count with hand-solder-friendly footprint for prototype work. When designing with this device, remember that the 1.2 V core rail must be sequenced within 50 ms of the I/O rails to prevent I/O cell back-powering through ESD diodes. Use the Lattice iCEcube2 design suite for synthesis, place-and-route, and bitstream generation.
iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice
The Lattice Semiconductor iCE40UP5K-SG48 is an iCE40 UltraPlus low-power FPGA with 5280 Look-Up Tables (LUTs), 128 Kbit of dual-port block RAM, 1 Mbit of single-port RAM, and eight 16x16 DSP MAC blocks, housed in a 48-pin VFQFN exposed-pad (SG48) package. A Field Programmable Gate Array (FPGA) is a reconfigurable logic device that implements digital circuits through programmable interconnect and logic blocks. Within the semiconductor hierarchy, FPGAs sit alongside microcontrollers and ASICs as programmable silicon; the iCE40 UltraPlus family occupies the ultra-low-power end of the FPGA spectrum, targeting mobile, IoT, and AI/ML edge applications where milliwatts matter. Key features include two hard-IP SPI and two hard-IP I2C controllers that offload protocol handling from soft logic, two internal oscillators (10 kHz and 48 MHz) that eliminate external clock sources in cost-sensitive designs, three 24 mA constant-current RGB outputs with hard RGB PWM IP for direct LED drive, and dedicated DSP blocks with 16x16 multiply and 32-bit accumulate for lightweight neural network inference. Architecturally, the iCE40UP5K combines a 4-input LUT plus carry chain plus flip-flop fabric with 120 Kbit of distributed sysMEM block RAM and 1 Mbit SPRAM, a phase-locked loop (PLL) for clock synthesis, and low-power 1.2V core operation consistent with the family's positioning as the lowest-power machine learning solution in its class. Typical applications include sensor aggregation and pre-processing for mobile platforms, always-on AI/ML inference at the edge, and system management or bridge logic where two SPI and two I2C hard IPs reduce firmware complexity. The SG48 QFN footprint also suits compact boards such as the iCEBreaker open-source FPGA platform. Design consideration: use the SG48 package with QSPI flash configuration and account for the exposed thermal pad in PCB layout for reliable ground return. This page synthesizes distributor listings, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet.