5M240ZM68I5N vs 5M80ZM68I5N 比較
詳細な並列比較: 5M240ZM68I5N メーカー: Intel および 5M80ZM68I5N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5M240ZM68I5N | 5M80ZM68I5N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.25 | $4.15 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 240 | — |
| Number of Macrocells | 192 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Configuration Memory | Nonvolatile Flash | — |
| Package Type | TFBGA-68 | — |
| Number of Terminals | 68 (ball) | — |
| Package Code | TFBGA | — |
| Form of Terminal | Ball | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Industrial | — |
| JTAG Interface | TMS, TDI, TDO, TCK (Bank 1) | — |
| Programming Method | JTAG / in-system programmable | — |
| 電源電圧 | [DATA_NEEDED: VCCINT and VCCIO levels] | — |
| I/O Standards | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Compliant | Compliant |
| Lead Free | Yes | — |
| Family | — | MAX V |
| Macro Cells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| User I/O Pins | — | 52 |
| User Flash Memory | — | 160 bits |
| Core Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| パッケージ | — | 68-ball MBGA (5M80ZM68) |
| 動作温度 | — | -40C to +100C (Industrial) |
| Programming Interface | — | JTAG (IEEE 1149.1) + ISP |
| Operating Mode | — | Non-volatile, instant-on |
| Lead-Free / Halogen-Free | — | Yes / Unknown |