EP1810GC-35 vs EP1810JC-35 比較
詳細な並列比較: EP1810GC-35 メーカー: Altera および EP1810JC-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810GC-35 | EP1810JC-35 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $177.12 | $5.48 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Logic Family | Altera Classic EPLD | — |
| Technology | CMOS, UV-erasable EPROM cells | — |
| パッケージ | CPGA-68 (Ceramic Pin Grid Array, 68-pin) | — |
| ピン数 | 68 | — |
| Propagation Delay (tpd max) | 40 ns | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Macrocells | 16 | — |
| I/O Standard | TTL-compatible | — |
| Programming Method | UV erasure + EPROM programming | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | — |
| 電源電圧 | [DATA_NEEDED: VCC range] | — |
| 実装タイプ | Through Hole | Surface Mount (J-Lead) |
| RoHS ステータス | Not applicable (legacy ceramic package) | Compliant (per Altera listing) |
| Lead-Free Status | Not applicable | Lead-free (per distributor listing) |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) | — |
| Original Manufacturer | Altera Corporation (now Intel FPGA) | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| Propagation Delay (tpd) | — | 35 ns (max) |
| 最大クロック周波数 | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 動作温度範囲 | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |