EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester
部品番号: EP1810GC-35 ⚠ ラストタイムバイ| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $185.65 | $185.65 |
| 2 | $177.12 | $354.24 |
| 5 | $195 | $975.00 |
| 10 | $188.5 | $1,885.00 |
| 25 | $180 | $4,500.00 |
EP1810GC-35 概要
An EPLD (Erasable Programmable Logic Device) is a type of Programmable Logic Device (PLD) that uses UV-erasable EPROM cells to store the user's logic configuration. EPLDs sit in the broader taxonomy of programmable logic devices, between simple SPLDs/PLAs and more complex CPLDs/FPGAs. The EP1810GC-35 belongs to the Classic EPLD family, which targets glue-logic integration in systems where deterministic timing and short propagation delays matter more than raw logic density. CPLDs and FPGAs are now the mainstream alternatives, but classic UV EPLDs remain in service in long-lifecycle industrial, aerospace, and military programs.
Key specifications include 16 macrocells (industry-standard terminology for this family), a maximum propagation delay of 40 ns, TTL-compatible I/O, and a maximum clock frequency determined by the tpd figure. The CPGA68 ceramic package is a through-hole Pin Grid Array rated for the extended industrial and military temperature range, which is the reason CPGA variants remain popular for high-reliability applications. The device is programmed via the Altera classic programming algorithm and erased by exposing the quartz window to UV light, allowing multiple reprogramming cycles during development.
Typical applications include bus-interface glue logic, address decoding, state-machine implementation, and interrupt prioritisation in legacy industrial controllers, avionics subsystems, and military-grade embedded systems. The deterministic 40 ns delay and TTL I/O make it straightforward to use as a drop-in replacement for discrete 74-series glue logic, while consolidating dozens of packages into a single programmable device.
Designers should verify the supply voltage and I/O standard against the original system specification before substituting a CPLD, since newer CMOS-only families require different programming voltages. For long-life-cycle programs, sourcing the EP1810GC-35 through Rochester Electronics ensures continued support and traceability under the original Altera datasheet specification. This page consolidates verified distributor pricing, pin-compatible alternatives, and design notes not found on a single OEM page.
ドロップイン代替品: EP1810GC-35 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1810GC-35 （同一形状・フットプリント） — 相違点: Package, Mounting Type, Technology, Operating Temperature, Process Technology.
クイック比較ツール — 並列比較する代替部品を選択:
EP1810GC-45
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP1810GM-45
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP1810GC-35 最大定格＆電気的特性
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Logic Family | Altera Classic EPLD |
| Technology | CMOS, UV-erasable EPROM cells |
| パッケージ | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| ピン数 | 68 |
| Propagation Delay (tpd max) | 40 ns |
| Maximum Inputs | 64 |
| Maximum Outputs | 48 |
| Macrocells | 16 |
| I/O Standard | TTL-compatible |
| Programming Method | UV erasure + EPROM programming |
| 実装タイプ | Through Hole |
| RoHS ステータス | Not applicable (legacy ceramic package) |
| Lead-Free Status | Not applicable |
| Manufacturer (current source) | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | Altera Corporation (now Intel FPGA) |
EP1810GC-35 cpga-68 (ceramic pin grid array, 68-pin) ピン配置ガイド
EP1810GC-35 (cpga-68 (ceramic pin grid array, 68-pin) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP1810GC-35.
詳細は データシート をご参照ください。
主な用途
EP1810GC-35 の用途: 6 件s: Legacy Industrial Glue Logic, Avionics and Military Subsystems, State-Machine and Decoder Consolidation, Bus-Interface and Chip-Select Generation, Test and Measurement Front-End Logic, Long-Life-Cycle Spares and Refurbishment.
Legacy Industrial Glue Logic
The EP1810GC-35 consolidates dozens of 74-series glue-logic packages into a single 16-macrocell EPLD with a deterministic 40 ns propagation delay. In long-life industrial controllers and machine-tool retrofits, it performs address decoding, chip-select generation, and interrupt prioritisation where the original Altera Classic EPLD footprint must remain. The TTL-compatible I/O mates directly with legacy 5 V logic, and the UV-erasable window lets field engineers re-burn the configuration during commissioning. Compared with a modern MAX V CPLD, the EP1810GC-35 keeps the PCB artwork and Altera programming flow intact, eliminating costly requalification of long-lifecycle industrial systems. This is the canonical use case for the part.
おすすめ
Avionics and Military Subsystems
The EP1810GC-35's ceramic CPGA-68 package and Altera EPLD architecture have made it a fixture in avionics line-replaceable units and military embedded subsystems. The hermetic ceramic package withstands the thermal-cycling and vibration profiles of DO-160 and MIL-STD-810 testing, while the 40 ns tpd is fast enough for ARINC 429 and MIL-STD-1553 bus-interface glue. Sourcing through Rochester Electronics preserves the Altera original-spec traceability required for FAA and military airworthiness programs. Designers should pair the EP1810GC-35 with the EP1810GM-45 for the same board's high-temperature zones, since both share the same die.
おすすめ
State-Machine and Decoder Consolidation
With 16 macrocells and up to 48 outputs, the EP1810GC-35 is well suited to replacing discrete state-machine boards built from 74LS/74HC flip-flops and PAL/GAL devices. Engineers typically burn Moore or Mealy state machines, address decoders, and custom instruction decoders into the EP1810, removing 8-15 small-scale integration packages from the BOM. The 40 ns propagation delay supports clock frequencies up to ~25 MHz in synchronous designs, which is sufficient for legacy 8/16-bit microprocessor glue. Rochester Electronics' continuing-source program guarantees that production volumes remain available across multi-year military and industrial programs.
おすすめ
Bus-Interface and Chip-Select Generation
In VMEbus, Multibus, and legacy ISA backplanes, the EP1810GC-35 generates chip-select, wait-state, and bus-arbitration signals with deterministic 40 ns timing. Its 64-input capacity is enough to decode full 24-bit address buses plus control signals, replacing multiple 74LS138 / 74LS139 decoder trees. The TTL-compatible I/O connects directly to bus transceivers without level shifting, simplifying board layout. Designers should add 4.7 kΩ pull-ups on unused inputs to avoid floating-pin oscillation, a common pitfall when migrating from a discrete decoder to a Classic EPLD.
おすすめ
Test and Measurement Front-End Logic
The EP1810GC-35 is used in legacy oscilloscope, logic-analyzer, and bench-instrument front-ends to generate range-decoding, channel-multiplexing, and trigger-conditioning logic. The deterministic 40 ns delay is short enough to keep jitter under one clock period at typical 25 MHz sample rates, while the 48 outputs drive front-panel relay matrices and attenuator ladders. The UV-erasable window allows calibration engineers to refine the configuration in the lab without discarding the device, which is a meaningful cost advantage over one-time-programmable PALs in low-volume instrumentation.
おすすめ
Long-Life-Cycle Spares and Refurbishment
Because the EP1810GC-35 was designed into military, aerospace, and industrial systems in the 1990s and early 2000s, it is still required as a long-life-cycle spare for in-service equipment. Refurbishment lines stock the EP1810GC-35 alongside the EP1810GC-45 and EP1810GM-45 so that field-replaceable units can be rebuilt without PCB redesign. Rochester Electronics' continuous-source wafer bank guarantees traceability and conformance to the original Altera datasheet, which is essential for FAA, EASA, and military airworthiness paperwork. Designers should treat the part as a 10-20 year availability window rather than a mainstream active component.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1810GC-35 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1810GC-45 | EP1810GM-45 | EP1810JC-35 |
|---|---|---|---|---|
| Brand | Altera (sourced via Rochester Electronics) | Altera (Rochester) | Altera (Rochester) | Altera (Rochester) |
| Package | CPGA-68 (ceramic Pin Grid Array) | CPGA-68 - same | CPGA-68 / PGA-68 - same | JLCC-68 - different footprint |
| Propagation Delay (tpd max) | 40 ns | 45 ns (+12.5%) | 45 ns (+12.5%) | 40 ns (same) |
| Macrocells | 16 | 16 (same) | 16 (same) | 16 (same) |
| Max Inputs / Outputs | 64 / 48 | 64 / 48 (same) | 64 / 48 (same) | 64 / 48 (same) |
| Temperature Grade | Industrial (CPGA ceramic) | Industrial (CPGA ceramic) | Military (-55C to +125C) | Industrial (JLCC ceramic) |
| Programming Method | UV-erasable EPROM | UV-erasable EPROM (same) | UV-erasable EPROM (same) | UV-erasable EPROM (same) |
主な差別化要因
- Fastest speed grade in the EP1810 Classic EPLD CPGA family （vs EP1810GC-45)
- Industrial-temperature CPGA ceramic at single-unit distributor availability （vs EP1810GM-45)
- Through-hole CPGA-68 vs surface-mount JLCC-68 alternative （vs EP1810JC-35)
設計ノート
Estimated: at 5 V VCC and typical 16-macrocell utilisation, the EP1810GC-35 draws approximately 80-120 mA ICC (Icc depends on the number of simultaneously-switching outputs and the toggle rate). Add a 0.1 uF decoupling capacitor close to each VCC pin pair and a bulk 10-47 uF tantalum on the supply rail. Designers migrating from 74LS glue logic should budget for higher quiescent current than the discrete implementation it replaces.
Unused EP1810GC-35 inputs must not be left floating; tie each unused input to VCC through a 4.7 kΩ pull-up resistor to prevent shoot-through current in the input buffer. Likewise, configure unused macrocells as outputs driving logic-low, or as inputs with the pull-up enabled. Floating inputs can cause ICC to rise by 20-40 mA and may trigger intermittent functional failures - a recurring support issue on legacy EPLD designs.
The CPGA-68 ceramic package has a low theta-JA (approximately 30-40 C/W in still air, depending on socket), so most EP1810GC-35 designs operate without a heatsink. However, in sealed military enclosures with no forced airflow, verify junction temperature by measuring case temperature and applying the package thermal resistance from the Altera datasheet. Estimated: a 100 mA ICC at 5 V with theta-JA of 35 C/W gives a 17.5 C rise above ambient - well within the 0 C to +70 C industrial range.
Mount the EP1810GC-35 in a through-hole CPGA socket (e.g., a 68-pin PGA socket with machined-pin contacts) to allow UV erasure and reprogramming. Avoid soldering the part directly to the PCB - field engineers must be able to remove the device for reprogramming. Place the quartz erasure window unobstructed above the package top surface, and reserve 25 mm vertical clearance above the board for the UV eraser lamp.
コンプライアンス情報
EP1810GC-35 is a legacy ceramic CPGA part predating RoHS; franchised distributor listings mark it 'Not applicable / Lead Free Status: Not applicable'. Reach and conflict-minerals status not stated in verified web data; not AEC-Q100 qualified (military grade handled by EP1810GM-45).
