EP1810GM883B vs EP1810JC-25 比較
詳細な並列比較: EP1810GM883B メーカー: Altera および EP1810JC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810GM883B | EP1810JC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $125.40 | $6.80 |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 48 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | 25 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable (windowed ceramic DIP) |
| 動作温度 | -55 °C to +125 °C (Military, MIL-STD-883B) | -40 °C to 85 °C (industrial, per distributor listings) |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| 実装タイプ | Through-hole (PGA socket or PCB through-hole) | Through-hole |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera/Intel Classic EPLD (EP1810 series) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| External Clock Inputs | — | 4 |
| パッケージ | — | 28-pin ceramic DIP (J) with quartz window |
| Erasure Method | — | UV light (windowed package) |
| RoHS ステータス | — | [DATA_NEEDED: RoHS compliance status] |
| ライフサイクル状態 | — | NRND (Not Recommended for New Designs) |