EP1810JC-25 vs EP1810JI-45 比較
詳細な並列比較: EP1810JC-25 メーカー: Intel および EP1810JI-45 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810JC-25 | EP1810JI-45 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $6.80 | $9.75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 動作温度 | -40 °C to 85 °C (industrial, per distributor listings) | -40 °C to +85 °C |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS EPROM |
| パッケージ | 28-pin ceramic DIP (J) with quartz window | — |
| 実装タイプ | Through-hole | — |
| Erasure Method | UV light (windowed package) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | — |
| ライフサイクル状態 | NRND (Not Recommended for New Designs) | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Configurable I/O Lines | — | 48 |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| 電源電圧 | — | 5 V (TTL compatible) |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |