EP1810JC-25 vs EP1810JI-45 비교
다음의 상세 나란히 비교: EP1810JC-25 제조: Intel 및 EP1810JI-45 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC-25 | EP1810JI-45 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $6.80 | $9.75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | 50 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 동작 온도 | -40 °C to 85 °C (industrial, per distributor listings) | -40 °C to +85 °C |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS EPROM |
| 패키지 | 28-pin ceramic DIP (J) with quartz window | — |
| 실장 유형 | Through-hole | — |
| Erasure Method | UV light (windowed package) | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | — |
| 수명 주기 상태 | NRND (Not Recommended for New Designs) | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Configurable I/O Lines | — | 48 |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| 공급 전압 | — | 5 V (TTL compatible) |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |