EP1810LC-20T - Classic CPLD 900 Gates 48 Macrocells 5V PLCC-68 | Intel
部品番号: EP1810LC-20T ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP1810LC-20T 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the programmable-logic hierarchy between simple PLDs (PAL/GAL) and high-density FPGAs. The Classic EPLD architecture combines AND/OR array logic with a fixed, deterministic interconnect fabric and an EEPROM-based configuration memory, giving designers a glue-logic alternative to discrete TTL or CMOS gates for decoder, bus-interface, state-machine, and peripheral-control functions.
Key features of the EP1810LC-20T include 48 macrocells organized across four Logic Array Blocks (LABs) of 12 macrocells each, a sum-of-products (product-term) architecture with both combinatorial and registered (D-type flip-flop) outputs, and a JTAG-compliant IEEE 1149.1 boundary-scan interface for in-system programming and test. The 5 V core simplifies interface to legacy 5 V TTL logic without level shifters, and the PLCC-68 package offers socket-friendly field upgrades for prototype and production environments.
Architecturally, the device uses Altera's Classic MAX-style interconnect: each macrocell distributes product terms across the LAB and feeds an I/O pin through a tri-state output buffer. Configuration is stored in on-chip EEPROM, eliminating the need for an external boot PROM and providing instant-on operation at power-up. Programming is performed via the JTAG port or the older Altera Master/Slave serial interface.
Typical applications include 5 V bus-interface and address decoding in industrial control backplanes, glue-logic replacement for legacy 74-series designs, I/O expansion and timing-control blocks, state-machine and protocol-bridging logic, and small-scale register/buffer functions in test equipment. The non-volatile EEPROM configuration also makes it well-suited to safety-critical or boot-loader designs that must come up in a known state.
When designing with the EP1810LC-20T, ensure that all unused I/O pins are configured as outputs driving a defined logic level or as inputs with internal pull-ups enabled, to avoid supply-current transients. Decouple VCC with 0.1 microfarad ceramic capacitors placed within 5 mm of each VCC/GND pair, and observe the device's 5 V absolute-maximum rating when hot-plugging into mixed-voltage buses.
This page synthesizes distributor pricing, drop-in alternatives from the Altera Classic family, and practical design notes that go beyond the manufacturer datasheet, including pin-compatibility flags and engineering guidance for migrating to modern MAX-series replacements.
ドロップイン代替品: EP1810LC-20T — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1810LC-20T （同一形状・フットプリント） — 相違点: Mounting Type, Technology, Package, Operating Temperature, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EP1810LC-20
✅ ドロップイン✓ 在庫あり
$7.85 / 個
データシートを見る →EP1810LC-25
✅ ドロップイン✓ 在庫あり
$8.4 / 個
データシートを見る →EP1810LC-15
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP1810GM883B
✅ ドロップイン✓ 在庫あり
$125.4 / 個
データシートを見る →EP1810GM883
✅ ドロップイン✓ 在庫あり
$175 / 個
データシートを見る →EP1810GI-45
✅ ドロップイン✓ 在庫あり
$56.4 / 個
データシートを見る →EP1810LC-20T 最大定格＆電気的特性
| Family | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 900 gates |
| Macrocells | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells |
| Maximum Toggle Frequency | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | 20 ns |
| Supply Voltage (VCC) | 5 V |
| Package Type | PLCC-68 (J-lead) |
| 実装タイプ | Surface Mount (socket-compatible) |
| Configuration Memory | On-chip EEPROM (non-volatile) |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| 動作温度 | 0C to +70C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) |
| RoHS ステータス | Non-compliant (legacy 5V PLCC) |
EP1810LC-20T ピン構成
| ピン 1 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 2 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 3 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 4 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 5 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 6 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 7 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 8 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 9 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 10 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 11 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 12 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 13 | GND — Ground |
| ピン 14 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 15 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 16 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 17 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 18 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 19 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 20 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 21 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 22 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 23 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 24 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 25 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 26 | GND — Ground |
| ピン 27 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 28 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 29 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 30 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 31 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 32 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 33 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 34 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 35 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 36 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 37 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 38 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 39 | GND — Ground |
| ピン 40 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 41 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 42 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 43 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 44 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 45 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 46 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 47 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 48 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 49 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 50 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 51 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 52 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 53 | GND — Ground |
| ピン 54 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 55 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 56 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 57 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 58 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 59 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 60 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 61 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 62 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 63 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 64 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 65 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 66 | I/O — User I/O pin (macrocell bidirectional) |
| ピン 67 | VCC — 5V supply voltage |
| ピン 68 | VCC — 5V supply voltage |
主な用途
EP1810LC-20T の用途: 6 件s: 5V Bus Address Decoding, Glue Logic Replacement for 74-Series TTL, State Machine Controllers, I/O Expansion and Bus Bridging, Legacy Industrial Control Systems, Prototype and Education Boards.
5V Bus Address Decoding
The EP1810LC-20T is well-suited for 5 V bus address decoding in industrial backplanes and legacy ISA-style systems. Its 48 macrocells provide enough product-term logic to implement multi-chip-select decoders for memory banks and peripherals, while the 5 V VCC interface eliminates the need for level shifters when bridging to 5 V TTL devices. The 20 ns pin-to-pin delay suits system clocks up to 25 MHz. Unlike 3.3 V CPLDs, the EP1810LC-20T directly drives TTL loads without pull-ups, simplifying PCB routing and reducing BOM cost in 5 V-only designs.
おすすめ
Glue Logic Replacement for 74-Series TTL
Engineers use the EP1810LC-20T to consolidate dozens of 74LS/74HC glue-logic gates, muxes, and flip-flops into a single non-volatile device, freeing PCB area and reducing assembly cost. The Classic EPLD's product-term architecture maps directly onto standard SSI/MSI TTL functions, allowing straightforward migration from legacy schematics. With 48 macrocells the device can absorb a typical decode-and-control block in a single chip. Its on-chip EEPROM ensures the device powers up in the correct state, eliminating the boot-time race conditions possible with discrete flip-flop implementations.
おすすめ
State Machine Controllers
The EP1810LC-20T's registered macrocell output with D-type flip-flops makes it a strong fit for state-machine controllers in industrial controllers, vending machines, and test equipment. Each macrocell can implement one Moore or Mealy state bit, allowing the device to host a 48-state machine with combinatorial next-state logic in a single chip. The 50 MHz toggle frequency supports state-machine clock rates up to 40 MHz after timing margin. Combined with JTAG in-system programming, designers can iterate state tables quickly during development without replacing the device or reworking the PCB.
おすすめ
I/O Expansion and Bus Bridging
In I/O expansion and bus-bridging applications, the EP1810LC-20T can serve as a parallel-to-serial converter, bit-banging interface, or low-speed bus arbiter. The 68-pin PLCC provides up to 56 user I/O pins (after power and JTAG pins), sufficient for 16-bit data plus 8-bit address interfaces typical of legacy microcontrollers. The Classic EPLD's deterministic interconnect guarantees fixed propagation delays regardless of logic placement, simplifying worst-case timing analysis. Designers pair it with an MCU or DSP that lacks sufficient I/O, offloading peripheral control logic to the CPLD.
おすすめ
Legacy Industrial Control Systems
The EP1810LC-20T remains in service across long-life industrial control systems (PLCs, motor drives, instrumentation) that were designed in the 1990s and require field replacements. Its 5 V PLCC-68 footprint, EEPROM non-volatility, and 20 ns logic delay match the original design exactly. The Classic EPLD's tolerance to electrical noise and industrial-temperature variants (such as the EP1810GI-45) make it suitable for factory-floor environments. For systems with 10+ year field-life support obligations, the EP1810LC-20T is often the only drop-in option without an expensive board redesign.
おすすめ
Prototype and Education Boards
The EP1810LC-20T is widely used in university digital-logic laboratories and prototype boards because its PLCC-68 package fits a standard IC socket, allowing students to remove and reprogram the device repeatedly. Programming via JTAG with the legacy Altera ByteBlaster cable and MAX+PLUS II or Quartus software makes it accessible for teaching. The Classic EPLD's transparent architecture shows students direct mapping from logic equations to silicon, unlike modern LUT-based FPGAs that abstract away the underlying structure. Its low I/O count (56 user pins) and modest gate capacity keep introductory design examples tractable.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1810LC-20T — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1810LC-20 | EP1810LC-25 | EP1810LC-15 | EP1810GM883B | EP1810GI-45 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | PLCC-68 | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same | PLCC-68 - same |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 25 ns (+25%) | 15 ns (-25%) | 20 ns | 45 ns (+125%) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Military MIL-883B | Industrial (-40C to +85C) |
| Shipping Format | Tape & Reel | Tube | Tube or Tape & Reel | Tube or Tape & Reel | Tube | Tube |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete (military stock only) | Obsolete |
主な差別化要因
- Tape-and-reel shipping format for automated assembly （vs EP1810LC-20)
- Balanced speed grade for 5V industrial designs （vs EP1810LC-25)
- Commercial temperature grade at lower cost （vs EP1810GM883B)
設計ノート
The EP1810LC-20T draws ICC in the range of 50-200 mA from a 5 V supply, with peaks during JTAG programming that can reach 300 mA. Decouple each VCC pin (1, 34, 68) with a 0.1 microfarat X7R ceramic capacitor placed within 5 mm of the pin, and add a single 10 microfarad tantalum or low-ESR electrolytic bulk capacitor at the board entry point. Inadequate decoupling causes voltage droops during EEPROM writes that can corrupt configuration. Place a ferrite bead in series with VCC if the device shares a supply with switching regulators.
The PLCC-68 socket footprint requires a through-hole PLCC socket (AMP 821574-1 or equivalent) for prototype work and field replacement. For production, hand-soldering or reflow of PLCC-68 is feasible but recommended only with a land pattern that includes extended pads. Keep all signal traces at least 3 mm from the socket body to avoid shorts, and route JTAG signals (TMS, TCK, TDI, TDO, nTRST) as a star from the JTAG connector directly to the device pins, with no stubs. Add a 10 kilohm pull-up on nCE (if exposed) to prevent accidental configuration at power-up.
Three common pitfalls when designing with the EP1810LC-20T: (1) leaving unused I/O pins floating creates output-driver contention and excess ICC; configure all unused pins in the MAX+PLUS II / Quartus software as outputs driving ground, or as inputs with internal pull-ups enabled. (2) The device is not hot-pluggable - if a partially inserted socket connects VCC before GND, latch-up can occur; add sequencing circuitry if hot-swap is required. (3) Do not exceed the 5 V absolute-maximum rating on any I/O pin, even briefly during system bring-up; use 5 V-tolerant buffers when interfacing to higher-voltage buses.
コンプライアンス情報
Legacy 5 V PLCC part produced before RoHS; uses tin-lead (SnPb) lead finish. Reach and conflict-mineral status not stated in manufacturer documentation. AEC-Q100 qualification not applicable for commercial-grade programmable logic in industrial/consumer use cases; military variants (EP1810GM883B) follow MIL-883B screening instead.
