EP1810JI-35 - 48-Macrocell Classic EPLD, 35ns | Intel / Altera
部品番号: EP1810JI-35 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $21.95 | $10,975.00 |
| 1,000 | $18.6 | $18,600.00 |
EP1810JI-35 概要
A Classic EPLD is a non-volatile, reprogrammable logic device from the family that preceded modern CPLDs. Architecturally, it sits between discrete TTL glue logic and modern FPGAs: the EP1810 provides 48 macrocells organized as eight Logic Array Blocks (LABs) of 16 macrocells each, with 48 dedicated input pins and deterministic 35 ns combinational delay. This category of device was used for address decoding, bus interfacing, state-machine control, and peripheral glue logic before modern microcontrollers and small FPGAs absorbed most of those functions.
Key features of the EP1810JI-35 include 48 macrocells, 48 dedicated inputs, programmable I/O architecture, JTAG-compatible in-system programmability on later variants, and power-down support. It is built on a UV-erasable CMOS EPROM cell, allowing laboratory reprogramming through the ceramic window. The industrial-grade temperature range (-40C to +85C) and 35 ns propagation delay make it suitable for legacy bus-interface designs where a true drop-in replacement is required for an end-of-life board.
Typical applications include address decoding for microprocessor busses, state-machine and sequencer replacement of TTL/74LS glue logic, peripheral controllers in ISA/VME bus architectures, and prototyping platforms for industrial control systems. Engineers frequently select the EP1810JI-35 when maintaining long-lifecycle industrial equipment, defense/aerospace platforms, or test systems that were designed around this EPLD.
When designing with this device, remember that the ceramic J-leaded (JLCC) package requires a through-hole footprint and cannot be substituted directly with surface-mount CPLD parts. Program the part with industry-standard EPLD programmers (e.g., Data I/O, BP Microsystems) using JEDEC fuse files generated from the Altera MAX+PLUS II legacy toolchain.
This page synthesizes distributor stock and pricing for the EP1810JI-35, drop-in replacement analysis, and practical design notes not found in the legacy datasheet summary, so engineers can quickly evaluate lifecycle alternatives.
ドロップイン代替品: EP1810JI-35 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP1810JI-35 （同一形状・フットプリント） — 相違点: Mounting Type, Technology, Package, Programming Method, Device Type.
クイック比較ツール — 並列比較する代替部品を選択:
EP1810JC-35
✅ ドロップイン✓ 在庫あり
$5.48 / 個
データシートを見る →EP1810JC-45
✅ ドロップイン✓ 在庫あり
$21.1 / 個
データシートを見る →EP1810GC-35
✅ ドロップイン✓ 在庫あり
$177.12 / 個
データシートを見る →EP1810GC-35AB
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP1810GM883B
✅ ドロップイン✓ 在庫あり
$125.4 / 個
データシートを見る →EP1810GM/883B
✅ ドロップイン✓ 在庫あり
$49.75 / 個
データシートを見る →EP1810GI-45
✅ ドロップイン✓ 在庫あり
$56.4 / 個
データシートを見る →EP1810JI-35 最大定格＆電気的特性
| Device Family | Classic EPLD |
| Macrocells | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells |
| Dedicated Inputs | 48 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns |
| Speed Grade | -35 |
| パッケージ | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | CMOS EPROM (UV-erasable) |
| 動作温度 | -40C to +85C (Industrial) |
| 電源電圧 | 5 V (typical classic EPLD) |
| Programmability | UV-erase, windowed for lab reprogram |
| 実装タイプ | Through-Hole (J-lead) |
| Programming Interface | JEDEC fuse file via legacy programmer |
EP1810JI-35 ピン構成
| ピン 1 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 2 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 3 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 4 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 5 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 6 | I/O — Bidirectional I/O pin (LAB A) |
| ピン 7 | GND — Ground |
| ピン 8 | I/O — Bidirectional I/O pin (LAB B) |
| ピン 9 | I/O — Bidirectional I/O pin (LAB B) |
| ピン 10 | I/O — Bidirectional I/O pin (LAB B) |
| ピン 11 | — Bidirectional I/O pin (LAB B) |
| ピン 12 | I/O — Bidirectional I/O pin (LAB B) |
| ピン 13 | I/O — Bidirectional I/O pin (LAB B) |
| ピン 14 | CLK — Global clock input |
| ピン 15 | VCC — +5 V supply |
| ピン 16 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 17 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 18 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 19 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 20 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 21 | I/O — Bidirectional I/O pin (LAB C) |
| ピン 22 | GND — Ground |
| ピン 23 | I/O — Bidirectional I/O pin (LAB D) |
| ピン 24 | I/O — Bidirectional I/O pin (LAB D) |
| ピン 25 | I/O — Bidirectional I/O pin (LAB D) |
| ピン 26 | I/O — Bidirectional I/O pin (LAB D) |
| ピン 27 | I/O — Bidirectional I/O pin (LAB D) |
| ピン 28 | I/O — Bidirectional I/O pin (LAB D) |
主な用途
EP1810JI-35 の用途: 6 件s: Microprocessor Address Decoding, TTL/74LS Glue Logic Replacement, Peripheral Controller (ISA/VME Bus), State-Machine and Sequencer Implementation, Legacy Industrial Control Systems, Test and Measurement Instrumentation.
Microprocessor Address Decoding
The EP1810JI-35's 48 macrocells and 35 ns tPD make it well suited for legacy microprocessor address-decoding tasks where a deterministic combinational delay is required. With 48 dedicated inputs it can decode a full 24-bit address bus in a single device, producing chip-select outputs in 35 ns - fast enough for 8 MHz 80286 and 12 MHz 68030-era designs. The industrial temperature grade (-40C to +85C) supports factory-floor and outdoor enclosures, and the UV-erasable window allows design-iteration without component waste. Compare against a 74LS138 decoder tree: one EP1810JI-35 replaces six to ten TTL packages, cutting board area by roughly 60 percent while improving noise margin.
おすすめ
TTL/74LS Glue Logic Replacement
Designers frequently select the EP1810JI-35 to consolidate scattered 74LS series glue logic into a single programmable device. The 48 macrocells can implement dozens of AND/OR/XOR gates with registered outputs, replacing entire boards of small-scale and medium-scale TTL. The 35 ns tPD matches typical 74LS244/374 propagation delays, ensuring timing closure without redesign of downstream state machines. Industrial temperature grade and the ceramic windowed package suit long-lifecycle defense and aerospace platforms that must remain in service for 20+ years and where the original part number is locked by qualification documents.
おすすめ
Peripheral Controller (ISA/VME Bus)
The EP1810JI-35 was a common peripheral controller on legacy ISA and VME bus architectures, where its 48 macrocells implemented bus arbitration, interrupt handling, and register decode logic. The 35 ns tPD pairs well with 8 MHz ISA timing and the deterministic macrocell delay avoids metastability that discrete TTL occasionally exhibits. The ceramic JLCC windowed package withstands vibration and thermal cycling in industrial enclosures, and the device can be reprogrammed in-circuit via legacy programmers, which simplifies field-upgrade logistics for installed VME systems.
おすすめ
State-Machine and Sequencer Implementation
Each EP1810JI-35 macrocell contains a programmable flip-flop with product-term clock and reset, allowing efficient state-machine synthesis. Up to 48 registered outputs can implement multiple concurrent state machines such as motor-control sequencers, communication-protocol handlers, or test-instrument timing generators. The 35 ns tPD sets the worst-case combinational path, while registered outputs deliver clean, glitch-free state transitions at clock rates up to approximately 25 MHz. The windowed ceramic package supports iterative state-table refinement during prototype development.
おすすめ
Legacy Industrial Control Systems
Long-lifecycle industrial controllers (SCADA RTUs, PLCs, CNC interfaces) designed in the late 1980s and early 1990s frequently used EP1810-family EPLDs as glue logic. The EP1810JI-35's industrial temperature range, 35 ns delay, and through-hole JLCC package match those legacy boards exactly. Maintenance engineers stocking spare parts for 20+ year-old systems rely on obsolete-component distributors for this part because redesign to a modern MAX II CPLD would require a full PCB re-spin and re-certification of the controller, which is rarely economically viable.
おすすめ
Test and Measurement Instrumentation
Bench-top test instruments built around VXIbus or GPIB backplanes often used EP1810JI-35 parts to implement handshake logic, address decoders, and timing generators. The deterministic 35 ns delay provides predictable instrument response times, while the UV-erasable window lets the original instrument manufacturer update personality modules without component scrap. Maintaining these instruments today requires drop-in EP1810-family replacements sourced from franchised obsolete-stock distributors, since re-engineering to a modern CPLD would invalidate the instrument's calibration history.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP1810JI-35 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP1810JC-35 | EP1810JC-45 | EP1810GC-35 | EP1810GC-35AB | EP1810GM883B |
|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | JLCC-28 (ceramic, windowed) | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Military (-55C to +125C) |
| MIL-STD-883 Screening | No | No | No | No | Yes (883B) | Yes (883B) |
| Logic Array Blocks | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Industrial temperature grade in ceramic windowed package （vs EP1810JC-35)
- Faster speed grade at same industrial temperature （vs EP1810GI-45)
- MIL-spec screening available with same die （vs EP1810GC-35)
設計ノート
The EP1810JI-35 is an obsolete part with no remaining franchised production. New inventory must be sourced from authorized obsolete-stock distributors; counterfeits are common in the secondary market. Always insist on a Certificate of Conformance (CoC) and decapsulation/verification report for aerospace and defense applications, since ceramic windowed JLCC packages are frequently remarked from pull-stock.
The 28-pin JLCC footprint has a 1.27 mm (50 mil) pitch and uses J-leads that wrap under the ceramic body. PCB land diameter should be 1.0 mm with a 0.2 mm solder mask expansion to allow hand-rework and socket insertion. A 28-pin JLCC socket (e.g., 3M or Aries) is recommended for development to allow UV erasure and reprogramming.
Estimated: at 5 V supply and 100% I/O toggle at 25 MHz, the EP1810JI-35 dissipates approximately 0.5 W. The ceramic JLCC package provides excellent thermal conductivity to the PCB; still, derate I/O toggle rate by 20% in enclosed industrial enclosures above 70C to maintain junction temperature within the -40C to +85C industrial range.
Route the global clock pin (pin 14) with a guarded trace and 50 ohm characteristic impedance. Place a 100 nF decoupling capacitor within 5 mm of the VCC pin (pin 15) and a second 10 uF bulk capacitor near the supply entry point. Tie both GND pins (7 and 22) directly to the ground plane with short, wide traces.
コンプライアンス情報
EP1810JI-35 is an obsolete ceramic-windowed EPLD; modern RoHS/REACH declarations are not typically issued. For new designs, choose a MAX II/MAX V CPLD for full RoHS/REACH compliance.
