EP1M120F484I6M vs EP1M120F48I6 比較
詳細な並列比較: EP1M120F484I6M メーカー: Altera および EP1M120F48I6 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1M120F484I6M | EP1M120F48I6 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $325.00 | $158.00 |
| Family | Mercury (EP1M) | Mercury (Altera) |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | 120,000 |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | — |
| Package Code | BGA, 484 balls, Fine-pitch | BGA, Square |
| Package Shape | Square | — |
| Terminal Form | Ball | Ball |
| Temperature Grade | Industrial | Industrial |
| Speed Grade | -6 (slowest Mercury timing bin) | -6 |
| 電源電圧 | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| RoHS ステータス | Compliant (M revision) | [DATA_NEEDED: RoHS status] |
| Logic Elements / Cells | — | 4800 |
| Total User I/O | — | 303 |
| Number of Pins / Terminals | — | 484 |
| パッケージ | — | 484-BBGA, FCBGA |
| 動作温度 | — | -40C to +100C |
| Core Voltage | — | 1.8 V |
| Transceiver Channels (max) | — | 8 channels at 1.25 Gbps; remaining 10 channels at <=1.0 Gbps |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, LVDS |
| メモリタイプ | — | Embedded SRAM / dual-port RAM blocks |