EP20K100EFC324-1N vs EP20K30EFC324-1 比較
詳細な並列比較: EP20K100EFC324-1N メーカー: Altera および EP20K30EFC324-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K100EFC324-1N | EP20K30EFC324-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $108.00 | $99.50 |
| Family | APEX-20KE | APEX-20KE (1.8V, LVDS) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 4160 | — |
| Typical Gates | 100,000 | [DATA_NEEDED: typical gate count] |
| Maximum User I/O | 246 | 128 |
| Embedded System Blocks (ESBs) | 53248 bits | — |
| パッケージ | 324-BGA (FineLine BGA) | 324-FBGA (FineLine BGA, 19x19 mm) |
| 動作温度 | 0 C to 85 C | 0C to +85C (commercial grade per Altera family spec) |
| Propagation Delay | 1.6 ns | — |
| Internal Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | — |
| I/O Standard Support | LVDS, SSTL, HSTL, LVTTL, LVCMOS | — |
| Process Technology | 0.15 µm all-layer copper CMOS | SRAM-based, 0.18 um |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming Technology | SRAM-based (volatile, requires configuration device) | — |
| MultiVolt I/O | 1.8 V core with 3.3 V / 5.0 V I/O support | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | APEX-20K |
| Logic Elements (typical) | — | 30,000 (30KLE) |
| Total RAM Bits | — | 24576 |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| 実装タイプ | — | Surface Mount |
| ピン数 | — | 324 |
| Temperature Grade | — | Commercial (per Altera family specification) |
| Configuration | — | Passive serial / passive parallel / JTAG |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | — | -1 |
| MSLレベル | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| PLLs | — | Up to 4 (per APEX-20KE family) |