EP20K100EFC324-1N vs EP20K30EFC324-1 비교
다음의 상세 나란히 비교: EP20K100EFC324-1N 제조: Altera 및 EP20K30EFC324-1 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP20K100EFC324-1N | EP20K30EFC324-1 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $108.00 | $99.50 |
| Family | APEX-20KE | APEX-20KE (1.8V, LVDS) |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 4160 | — |
| Typical Gates | 100,000 | [DATA_NEEDED: typical gate count] |
| Maximum User I/O | 246 | 128 |
| Embedded System Blocks (ESBs) | 53248 bits | — |
| 패키지 | 324-BGA (FineLine BGA) | 324-FBGA (FineLine BGA, 19x19 mm) |
| 동작 온도 | 0 C to 85 C | 0C to +85C (commercial grade per Altera family spec) |
| Propagation Delay | 1.6 ns | — |
| Internal Operating Frequency | 250 MHz | — |
| Core Voltage | 1.8 V | — |
| I/O Standard Support | LVDS, SSTL, HSTL, LVTTL, LVCMOS | — |
| Process Technology | 0.15 µm all-layer copper CMOS | SRAM-based, 0.18 um |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming Technology | SRAM-based (volatile, requires configuration device) | — |
| MultiVolt I/O | 1.8 V core with 3.3 V / 5.0 V I/O support | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | APEX-20K |
| Logic Elements (typical) | — | 30,000 (30KLE) |
| Total RAM Bits | — | 24576 |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| 실장 유형 | — | Surface Mount |
| 핀 수 | — | 324 |
| Temperature Grade | — | Commercial (per Altera family specification) |
| Configuration | — | Passive serial / passive parallel / JTAG |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | — | -1 |
| MSL 레벨 | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| PLLs | — | Up to 4 (per APEX-20KE family) |