EP20K600CB652C7ES vs EP20K600CB652C9N 比較
詳細な並列比較: EP20K600CB652C7ES メーカー: Altera および EP20K600CB652C9N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CB652C7ES | EP20K600CB652C9N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $195.00 | $128.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | 488 |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.15 µm CMOS | 0.15 micron all-layer copper CMOS |
| 動作温度 | 0 °C to +85 °C (commercial) | 0 C to 85 C (commercial) |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| PLLs | 4 | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | Loadable PLD (FPGA) |
| Typical Gates | — | 600,000 |
| パッケージ | — | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.8 V |
| Speed Grade | — | C9 (~1.48 ns propagation delay) |
| Architecture | — | MultiCore LUT + embedded system memory (ESB) |
| On-chip Memory | — | Embedded system memory blocks (dual-port RAM, FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) and serial/PROM configuration |
| Pin/Pin Compatibility | — | Pin-compatible with APEX 20KE devices of same package |
| Toolchain | — | Altera/Intel Quartus II (legacy APEX support) |
| MSLレベル | — | [DATA_NEEDED: MSL level] |