EP20K600CB652C7ES vs EP20K600CB652C9N 비교
다음의 상세 나란히 비교: EP20K600CB652C7ES 제조: Altera 및 EP20K600CB652C9N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP20K600CB652C7ES | EP20K600CB652C9N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $195.00 | $128.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | 488 |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.15 µm CMOS | 0.15 micron all-layer copper CMOS |
| 동작 온도 | 0 °C to +85 °C (commercial) | 0 C to 85 C (commercial) |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| PLLs | 4 | — |
| 실장 유형 | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | Loadable PLD (FPGA) |
| Typical Gates | — | 600,000 |
| 패키지 | — | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.8 V |
| Speed Grade | — | C9 (~1.48 ns propagation delay) |
| Architecture | — | MultiCore LUT + embedded system memory (ESB) |
| On-chip Memory | — | Embedded system memory blocks (dual-port RAM, FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) and serial/PROM configuration |
| Pin/Pin Compatibility | — | Pin-compatible with APEX 20KE devices of same package |
| Toolchain | — | Altera/Intel Quartus II (legacy APEX support) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |