EP20K600CB652C7ES vs EP20K600CB652C9N 对比
详细并排对比 EP20K600CB652C7ES 出自 Altera 和 EP20K600CB652C9N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K600CB652C7ES | EP20K600CB652C9N |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $195.00 | $128.00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | 488 |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.15 µm CMOS | 0.15 micron all-layer copper CMOS |
| 工作温度 | 0 °C to +85 °C (commercial) | 0 C to 85 C (commercial) |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| PLLs | 4 | — |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | Loadable PLD (FPGA) |
| Typical Gates | — | 600,000 |
| 封装 | — | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.8 V |
| Speed Grade | — | C9 (~1.48 ns propagation delay) |
| Architecture | — | MultiCore LUT + embedded system memory (ESB) |
| On-chip Memory | — | Embedded system memory blocks (dual-port RAM, FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) and serial/PROM configuration |
| Pin/Pin Compatibility | — | Pin-compatible with APEX 20KE devices of same package |
| Toolchain | — | Altera/Intel Quartus II (legacy APEX support) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |