EP2A25F672I-7 vs EP2A25F672C9N 比較
詳細な並列比較: EP2A25F672I-7 メーカー: Intel および EP2A25F672C9N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2A25F672I-7 | EP2A25F672C9N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $171.00 | $195.00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| System Gates | 900K (approximately) | Approx. 900000 |
| Logic Cells / Elements | 24,320 | — |
| Maximum Operating Frequency | 500 MHz | — |
| Process Technology | 0.15 um | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | — |
| パッケージ | 672-pin FC-FBGA | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| 実装タイプ | Surface Mount (Flip-Chip BGA) | Surface Mount (BGA) |
| Speed Grade | -7 | — |
| 動作温度 | -40C to +85C (Industrial) | 0 °C to +85 °C (commercial, C9 grade) |
| Temperature Grade | Industrial (I) | — |
| Configuration Method | JTAG, Passive Serial, Active Serial | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| RoHS ステータス | [DATA_NEEDED: rohs status] | Compliant (per distributor listings) |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Embedded Memory | ESBs (Embedded System Blocks) | Enhanced System Blocks (ESBs) for dual-port RAM |
| Logic Elements / Cells | — | 24320 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Seated Height (max) | — | 2.100 mm |
| Propagation Delay | — | 2.23 ns |
| Logic Family | — | CMOS |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |