EP2AGZ300FF35I3G vs EP2AGZ300FF35C4N 比較
詳細な並列比較: EP2AGZ300FF35I3G メーカー: Intel および EP2AGZ300FF35C4N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2AGZ300FF35I3G | EP2AGZ300FF35C4N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1,230.00 | $1,350.00 |
| Family | Arria II GZ | — |
| Logic Elements (LE) | 300000 | — |
| Number of User I/O | 554 (maximum) | — |
| Number of Transceivers | 8 | — |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Process Node | 40 nm | — |
| 動作温度 | -40C to +100 C (I3 industrial) | — |
| パッケージ | 1152-ball FBGA (FF35) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 電源電圧 | [DATA_NEEDED: core and I/O supply voltage values] | — |
| Embedded Memory (Mbits) | 16.4 | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | [DATA_NEEDED: number of DSP blocks] |
| PLLs | [DATA_NEEDED: number of PLLs] | [DATA_NEEDED: PLL count] |
| Memory Interfaces | DDR3, QDRII+, RLDRAM II | — |
| Configuration Method | Serial, Parallel, JTAG | — |
| RoHS ステータス | Compliant | Compliant (per Besenchips / DigiKey listing) |
| MSLレベル | 3 (168 hours) | — |
| Lead-Free | Yes | — |
| Series | — | Arria II GZ |
| Logic Elements | — | 298,000 |
| Logic Array Blocks (LABs) | — | 11,920 |
| Embedded Memory (bits) | — | 18,854,912 (~17.9 Mbit) |
| User I/O Count | — | 554 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Process Technology | — | 40 nm |
| Core Voltage | — | 0.9 V |
| Package Type | — | 1152-BBGA, FCBGA (flip-chip) |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | HBGA |
| Operating Temperature Grade | — | Commercial (C4 = 0C to +85C) |
| Configuration Memory | — | SRAM-based (volatile, requires boot device) |
| Transceivers | — | Multi-gigabit transceivers integrated |
| Lead-Free Status | — | Lead free (per Besenchips listing) |
| Maximum Operating Frequency | — | 500 MHz |