EP610PC-15 vs EP610JI-30 比較
詳細な並列比較: EP610PC-15 メーカー: Altera および EP610JI-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610PC-15 | EP610JI-30 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $17.50 | $9.40 |
| Family | Classic EPLD | Altera Classic EPLD (EP610) |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 300 gates | — |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS | — |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| パッケージ | PDIP-24 (plastic DIP, 24-pin) | CQCC28 (windowed ceramic JLCC, J-bend) |
| ピン数 | 24 pins | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, per EP610 family suffix convention) |
| 実装タイプ | Through-Hole (DIP) | Surface Mount (JLCC) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| 電源電圧 | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |