EP610PC-15 vs EP610JI-30 对比
详细并排对比 EP610PC-15 出自 Altera 和 EP610JI-30 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610PC-15 | EP610JI-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.50 | $9.40 |
| Family | Classic EPLD | Altera Classic EPLD (EP610) |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 300 gates | — |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS | — |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| 封装 | PDIP-24 (plastic DIP, 24-pin) | CQCC28 (windowed ceramic JLCC, J-bend) |
| 引脚数量 | 24 pins | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, per EP610 family suffix convention) |
| 安装类型 | Through-Hole (DIP) | Surface Mount (JLCC) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| 电源电压 | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |