EP910DI-35 vs EP9100C-30 比較
詳細な並列比較: EP910DI-35 メーカー: Altera および EP9100C-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DI-35 | EP9100C-30 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $35.20 | $7.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 48 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 30 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 24 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| パッケージ | CDIP-40 (Ceramic DIP with UV window) | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP |
| 実装タイプ | Through-Hole | Through-Hole (DIP) / Surface Mount (PLCC) |
| 動作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable (window) or OTP |
| Programming Method | EPROM programmer + JEDEC fuse map | JEDEC via Altera APU or compatible programmer |
| Erasure Method | UV light through quartz window | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: rohs_status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Logic Density | — | 900 usable gates (approx.) |
| Flip-Flops | — | 24 |
| Maximum Toggle Frequency (fMAX) | — | 62.5 MHz |
| I/O Standard | — | TTL-compatible |
| Military Grade Variant | — | EP9100C-30/883 (MIL-STD-883 compliant) |