EP910DI-35 vs EP910DC-35 比較

詳細な並列比較: EP910DI-35 メーカー: Altera および EP910DC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP910DI-35 EP910DC-35
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 有効 Obsolete
在庫状況 In Stock In Stock
単価(USD) $35.20 $10.95
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD EP910
Macrocells 24 24
Usable Gates 450 900 gates
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 12
Bidirectional I/O Pins 20 —
Total Pins 40 —
パッケージ CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (Ceramic DIP) with quartz window
実装タイプ Through-Hole —
動作温度 -40C to +85C (industrial) 0 °C to +70 °C (commercial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Programming Method EPROM programmer + JEDEC fuse map JEDEC fuse map via device programmer; UV erase
Erasure Method UV light through quartz window —
RoHS ステータス [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
最大クロック周波数 — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Lifecycle — Obsolete / last-time-buy from authorized distributors

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