EP910DI-35 vs EP910DC-35 비교

다음의 상세 나란히 비교: EP910DI-35 제조: Altera 및 EP910DC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910DI-35 EP910DC-35
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $35.20 $10.95
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD EP910
Macrocells 24 24
Usable Gates 450 900 gates
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 12
Bidirectional I/O Pins 20 —
Total Pins 40 —
패키지 CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (Ceramic DIP) with quartz window
실장 유형 Through-Hole —
동작 온도 -40C to +85C (industrial) 0 °C to +70 °C (commercial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Programming Method EPROM programmer + JEDEC fuse map JEDEC fuse map via device programmer; UV erase
Erasure Method UV light through quartz window —
RoHS 상태 [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
최대 클록 주파수 — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Lifecycle — Obsolete / last-time-buy from authorized distributors

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