EP910DI-35 vs EP910ILC-15 比較
詳細な並列比較: EP910DI-35 メーカー: Altera および EP910ILC-15 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DI-35 | EP910ILC-15 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $35.20 | $16.10 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | — |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| パッケージ | CDIP-40 (Ceramic DIP with UV window) | 44-pin PLCC (J-lead) |
| 実装タイプ | Through-Hole | Surface Mount (SMT) |
| 動作温度 | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Series | — | EP910 |
| Logic Gates | — | 450 |
| User I/O Pins | — | 36 |
| Maximum Operating Frequency | — | 83.33 MHz |
| 電源電圧 | — | 5 V |
| メモリタイプ | — | EPROM (UV-erasable) |
| Propagation Class | — | -15 speed grade |
| Storage Condition | — | Dry cabinet, humidity-controlled |