EP910DI-35 vs EP910ILC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-35 sa pamamagitan ng Altera at EP910ILC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DI-35 | EP910ILC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | — |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| Packhaging | CDIP-40 (Ceramic DIP with UV window) | 44-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (SMT) |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM | — |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Series | — | EP910 |
| Logic Gates | — | 450 |
| User I/O Pins | — | 36 |
| Maximum Operating Frequency | — | 83.33 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Uri ng Memory | — | EPROM (UV-erasable) |
| Propagation Class | — | -15 speed grade |
| Storage Condition | — | Dry cabinet, humidity-controlled |