EP910LC-40H vs EP910ILC-25 比較
詳細な並列比較: EP910LC-40H メーカー: Altera および EP910ILC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910LC-40H | EP910ILC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $9.95 |
| Family | Classic EPLD (EP910) | EP910 Classic EPLD |
| Macro Cells | 24 | — |
| Usable Gates | 450 | — |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | 25 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM (UV-erasable) |
| パッケージ | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | 44-pin JLCC (windowed ceramic) |
| 実装タイプ | Through-Hole (THT) | Surface Mount |
| 動作温度 | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | -40C to +85C (industrial) |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | — |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| RoHS ステータス | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | non_compliant (ceramic windowed package) |
| Macrocells | — | 24 |
| User I/O Pins | — | 36 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| 電源電圧 | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| ライフサイクル状態 | — | Obsolete - last time buy was late 1990s |