EP910PI-30T - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
部品番号: EP910PI-30T ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
EP910PI-30T 概要
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that retains its configuration without external memory and is electrically erasable via UV exposure (windowed packages) or, in later erasable variants, electrically in-circuit. Within the broader component taxonomy, an EPLD sits below a CPLD (Complex PLD) and well below an FPGA in density, but offers faster deterministic pin-to-pin timing and instant-on behaviour, making EPLDs ideal for address decoding, bus interfacing, and control-logic replacement of discrete TTL/CMOS gates.
Key features of the EP910PI-30T include 24 macrocells with configurable D/T/JK flip-flops, 30ns combinational propagation delay (tPD), 20ns register (clock-to-output) delay, and ten dedicated input pins feeding an AND-OR-NOT sum-of-products structure. The device operates from a single 5V supply (VCC = 4.75V to 5.25V), supports in-system 100% generic testability, and is fully compatible with the Altera MAX+PLUS II Classic device development flow. The Classic architecture gives predictable, deterministic timing because each macrocell has a fixed product-term allocation.
Typical applications include TTL/CMOS gate and SSI/MSI replacement, address decoding for microprocessor buses, bus-interface glue logic, state-machine implementation, and industrial control systems. The ceramic-windowed PDIP package also supports field reprogramming after UV erasure during prototyping.
When designing with this part, plan for one extra I/O pin per macrocell versus the dedicated-pin count, and add a 0.1uF decoupling capacitor close to VCC. The 30ns speed grade is the slowest Classic EP910 variant and is intended for cost-sensitive legacy designs; for higher speed, choose EP910PC-25, EP910PC-20 or the EP910LC/LI -15/-20 grades.
This page synthesizes distributor pricing, verified drop-in alternatives from the Altera/Rochester Classic EPLD family, and practical design notes that supplement the original Altera datasheet.
ドロップイン代替品: EP910PI-30T — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910PI-30T （同一形状・フットプリント） — 相違点: Package, Supply Voltage (VCC), Propagation Delay (tPD), Technology, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
EP910PC-30
✅ ドロップイン✓ 在庫あり
$6.5 / 個
データシートを見る →EP910PI-25
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EP910PI-20
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EP910PI-15T
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EP910PI-12T
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP910PC-30T
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP910PI-30T 最大定格＆電気的特性
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Usable Gates | 480 |
| Dedicated Inputs | 10 |
| Propagation Delay (tPD) | 30 ns |
| Register (Clock-to-Output) Delay | 20 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable (windowed ceramic) |
| Package Type | 40-pin PDIP (ceramic windowed) |
| 実装タイプ | Through-Hole |
| 動作温度 | -40 C to +85 C (industrial) |
| Programming | Altera Classic device programmer / MAX+PLUS II flow |
EP910PI-30T ピン構成
| ピン 1 | I/O — Input/Output macrocell pin (MC1) |
| ピン 2 | I/O — Input/Output macrocell pin (MC2) |
| ピン 3 | I/O — Input/Output macrocell pin (MC3) |
| ピン 4 | I/O — Input/Output macrocell pin (MC4) |
| ピン 5 | I/O — Input/Output macrocell pin (MC5) |
| ピン 6 | I/O — Input/Output macrocell pin (MC6) |
| ピン 7 | I/O — Input/Output macrocell pin (MC7) |
| ピン 8 | I/O — Input/Output macrocell pin (MC8) |
| ピン 9 | I/O — Input/Output macrocell pin (MC9) |
| ピン 10 | I/O — Input/Output macrocell pin (MC10) |
| ピン 11 | I/O — Input/Output macrocell pin (MC11) |
| ピン 12 | I/O — Input/Output macrocell pin (MC12) |
| ピン 13 | I/O — Input/Output macrocell pin (MC13) |
| ピン 14 | I/O — Input/Output macrocell pin (MC14) |
| ピン 15 | I/O — Input/Output macrocell pin (MC15) |
| ピン 16 | I/O — Input/Output macrocell pin (MC16) |
| ピン 17 | I/O — Input/Output macrocell pin (MC17) |
| ピン 18 | I/O — Input/Output macrocell pin (MC18) |
| ピン 19 | I/O — Input/Output macrocell pin (MC19) |
| ピン 20 | GND — Ground (0V) |
| ピン 21 | I/O — Input/Output macrocell pin (MC20) |
| ピン 22 | I/O — Input/Output macrocell pin (MC21) |
| ピン 23 | I/O — Input/Output macrocell pin (MC22) |
| ピン 24 | I/O — Input/Output macrocell pin (MC23) |
| ピン 25 | I/O — Input/Output macrocell pin (MC24) |
| ピン 26 | IN — Dedicated input pin 1 |
| ピン 27 | IN — Dedicated input pin 2 |
| ピン 28 | IN — Dedicated input pin 3 |
| ピン 29 | IN — Dedicated input pin 4 |
| ピン 30 | IN — Dedicated input pin 5 |
| ピン 31 | IN — Dedicated input pin 6 |
| ピン 32 | IN — Dedicated input pin 7 |
| ピン 33 | IN — Dedicated input pin 8 |
| ピン 34 | IN — Dedicated input pin 9 |
| ピン 35 | IN — Dedicated input pin 10 |
| ピン 36 | NC — Not connected (per datasheet) |
| ピン 37 | NC — Not connected (per datasheet) |
| ピン 38 | NC — Not connected (per datasheet) |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | VCC — +5V supply voltage |
主な用途
EP910PI-30T の用途: 7 件s: TTL/CMOS Glue Logic Replacement, Microprocessor Address Decoding, Industrial Control State Machines, Bus Interface and Protocol Bridging, Legacy Avionics and Military Systems, Educational and Prototyping Platforms, Telecom Backplane Glue Logic.
TTL/CMOS Glue Logic Replacement
The EP910PI-30T replaces 4 to 8 discrete 74-series TTL/CMOS SSI/MSI packages on legacy 5V boards with a single 24-macrocell device, freeing PCB real-estate and reducing inventory. With 30ns tPD and 10 dedicated inputs, it can absorb random AND/OR/decoder logic that previously consumed two or three PALs. Industrial temperature operation (-40C to +85C) and a UV-erasable ceramic window make it ideal for prototypes that may need a logic revision after board bring-up.
おすすめ
Microprocessor Address Decoding
The EP910PI-30T is widely used to decode 24-bit address buses for memory-mapped peripherals, ROM/RAM chip-selects, and I/O port enables on 8086/68k/8051 systems. The deterministic 30ns tPD adds a known, fixed delay to the chip-select path, which simplifies worst-case timing analysis versus a discrete 74LS138/139 decoder. The 24 macrocells handle up to 8 to 12 chip-select outputs with overlapping address windows.
おすすめ
Industrial Control State Machines
Programmable state machines for industrial automation benefit from the EP910PI-30T's 24 flip-flop-equipped macrocells, which can encode Mealy/Moore machines with up to 16 million states. Industrial-temperature operation (-40C to +85C) and CMOS low-power consumption suit PLC digital I/O modules and motor-control interface boards. The 30ns tPD easily meets the cycle times of typical 1 to 5 MHz industrial scan loops.
おすすめ
Bus Interface and Protocol Bridging
The EP910PI-30T bridges legacy 8/16-bit microprocessor buses to peripheral ICs, generating wait-state timing, byte-swapping signals, and DMA acknowledge handshakes. With 30ns tPD and 20ns clock-to-output, the device sits comfortably between an 8 MHz 8051 bus and slower peripherals. Ten dedicated inputs accept multiple bus control lines, while the 24 macrocells implement combinational wait-state logic plus registered handshake flip-flops.
おすすめ
Legacy Avionics and Military Systems
Through-hole 40-pin ceramic-windowed PDIPs like the EP910PI-30T remain in service on legacy avionics, radar display controllers, and military communication boards because they meet shock, vibration, and temperature specs that newer plastic CPLDs cannot. Rochester Electronics continues to factory-fresh manufacture the part for sustainment programs. The 30ns tPD is well-matched to slower MIL-STD-1553 and ARINC 429 interface timing.
おすすめ
Educational and Prototyping Platforms
The EP910PI-30T is used in university digital-logic labs to teach programmable-logic concepts because the ceramic-windowed package allows students to erase and reprogram the device dozens of times during a semester. With 480 usable gates, students can implement complete 8-bit CPUs, UARTs, and traffic-light controllers on a single chip. The Altera Classic development flow supports schematic capture and AHDL entry, ideal for introductory VHDL/Verilog-adjacent teaching.
おすすめ
Telecom Backplane Glue Logic
Central-office telecom equipment deployed in the 1990s relies on EP910-family EPLDs for backplane address decoding, interrupt steering, and time-slot assignment on T1/E1 framers. The 30ns tPD easily meets the 8 kHz frame-rate timing, and the 5V CMOS interface is directly compatible with 1990s-era bus standards. Rochester Electronics continues to supply the EP910PI-30T for telecom OEMs needing long-life sustainment stock.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910PI-30T — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910PC-30 | EP910PI-25 | EP910PI-20 | EP910PI-15T | EP910PI-12T |
|---|---|---|---|---|---|---|
| Package | PDIP-40 (ceramic windowed) | PDIP-40 (ceramic windowed) - same | PDIP-40 (ceramic windowed) - same | PDIP-40 (ceramic windowed) - same | PDIP-40 (ceramic windowed) - same | PDIP-40 (ceramic windowed) - same |
| Brand | Altera (Rochester Electronics) | Altera (Rochester Electronics) - same brand | Altera (Rochester Electronics) - same brand | Altera (Rochester Electronics) - same brand | Altera (Rochester Electronics) - same brand | Altera (Rochester Electronics) - same brand |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 480 | 480 | 480 | 480 | 480 | 480 |
| tPD (max) | 30 ns | 30 ns | 25 ns | 20 ns | 15 ns | 12 ns |
| Clock-to-Output | 20 ns | 20 ns | 17 ns | 14 ns | 10 ns | 8 ns |
| Temperature Range | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Drop-in compatibility across the entire Classic EP910 family （vs EP910PC-30 / EP910PI-25 / EP910PI-20 / EP910PI-15T / EP910PI-12T)
- Industrial temperature range with UV-erasable reprogrammability （vs One-time-programmable (OTP) PAL/GAL equivalents)
- Deterministic, fixed product-term timing （vs Modern LUT-based CPLDs (MAX II, MAX V))
設計ノート
Decouple the EP910PI-30T with a 0.1uF ceramic capacitor placed within 5mm of the VCC pin (pin 40) and a 10uF tantalum bulk capacitor on the board-level 5V rail. The Classic EPLD's CMOS input structure draws switching current at every clock edge, and inadequate decoupling causes VCC droop that can lengthen tPD by 2 to 5 ns in noisy backplane environments. Add a ferrite bead if the EPLD shares a rail with motors or relay drivers.
Route the 10 dedicated inputs (pins 26-35) and the high-fanout global clock signals first, keeping them short and away from I/O switching lines. The 24 I/O macrocells (pins 1-19 and 21-25) can be placed on the board periphery for shortest package-to-connector stub lengths. Keep at least one ground via adjacent to every four I/O pins to provide a low-impedance return path for output switching currents.
Do not exceed 5.25V on VCC: the Classic EP910 EPROM cell does not have on-chip over-voltage protection and 6V applied for more than a few minutes can permanently damage the device. Always reprogram the device in a programmer socket, not on a live board, because the 12.5V VPP required for EPROM programming will back-drive the rest of the 5V logic. Use Altera's LogicMap or MAX+PLUS II to assign pin numbers before solder assembly to avoid rework.
The 30ns tPD speed grade limits the maximum toggle rate to approximately 16 MHz on registered outputs; for designs above 16 MHz select EP910PI-20 (20ns, 25 MHz) or EP910PI-15T (15ns, 33 MHz). Unused I/O pins should be configured as outputs driving low, not left floating, to avoid shoot-through current in the output structure that adds 1 to 2 mA per floating pin to quiescent supply current.
コンプライアンス情報
The Altera Classic EP910 family uses a ceramic-windowed DIP package with tin-lead (SnPb) leads, making it explicitly non-RoHS. The 'PI' industrial-temperature variant qualifies for many defense and aerospace sustainment programs that exempt SnPb parts under RoHS Annex III 7(c) and 7(a). Lead-free and halogen-free status for the EP910PI-30T were not stated in the verified distributor data and are listed as [DATA_NEEDED] in the specs array.
