EP910PI-20 vs EP910PI-30T 比較
詳細な並列比較: EP910PI-20 メーカー: Altera および EP910PI-30T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PI-20 | EP910PI-30T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $10.95 |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| パッケージ | PDIP-40 (PI suffix) | — |
| 実装タイプ | Through-Hole | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) | 4.75 V to 5.25 V (5 V nominal) |
| 動作温度 | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS, UV-erasable (windowed ceramic) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS status] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |