EP910PI-20 vs EP910PI-30T Vergleich
Detaillierter Direktvergleich von EP910PI-20 von Altera und EP910PI-30T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PI-20 | EP910PI-30T |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $10,95 |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| Gehäuse | PDIP-40 (PI suffix) | — |
| Montageart | Through-Hole | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) | 4.75 V to 5.25 V (5 V nominal) |
| Betriebstemperatur | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS, UV-erasable (windowed ceramic) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | 10 |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |