EPC16QC100II vs EPC16QC-100T 比較

詳細な並列比較: EPC16QC100II メーカー: Altera および EPC16QC-100T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPC16QC100II EPC16QC-100T
ブランド Altera Altera
カテゴリ Memory ICs Memory ICs
ライフサイクル状態 NRND Obsolete
在庫状況 In Stock In Stock
単価(USD) $10.75 $14.50
メモリタイプ FPGA Configuration PROM (Flash-based) Flash Configuration PROM (in-system programmable)
Memory Density 16 Mbit 16 Mbit (2 Mbyte)
Supported FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Mode FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) —
Programmability In-System Programmable via IEEE 1149.1 (JTAG) —
Cascade Support Yes (multi-PROM cascading supported) —
Core Supply Voltage 3.3 V —
I/O Tolerance 5 V tolerant configuration pins —
パッケージ 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
Package Dimensions 20 mm x 14 mm, 0.5 mm pitch —
Lead Finish Matte Tin (lead-free) —
動作温度 -40C to +85C (Industrial) [DATA_NEEDED: Operating temperature range]
MSLレベル 3 (per JEDEC J-STD-020) [DATA_NEEDED: Moisture sensitivity level]
RoHS ステータス Compliant unknown
Configuration Pins DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE —
Compression Support Yes (reduces on-PROM footprint vs uncompressed bitstream) —
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
電源電圧 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
Lead-Free — unknown
実装タイプ — Surface Mount

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