EPC16QC100II vs EPC16QC-100T 비교

다음의 상세 나란히 비교: EPC16QC100II 제조: Altera 및 EPC16QC-100T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPC16QC100II EPC16QC-100T
브랜드 Altera Altera
카테고리 Memory ICs Memory ICs
수명 주기 상태 NRND Obsolete
재고 상태 In Stock In Stock
단가 (USD) $10.75 $14.50
메모리 유형 FPGA Configuration PROM (Flash-based) Flash Configuration PROM (in-system programmable)
Memory Density 16 Mbit 16 Mbit (2 Mbyte)
Supported FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Mode FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous) —
Programmability In-System Programmable via IEEE 1149.1 (JTAG) —
Cascade Support Yes (multi-PROM cascading supported) —
Core Supply Voltage 3.3 V —
I/O Tolerance 5 V tolerant configuration pins —
패키지 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
Package Dimensions 20 mm x 14 mm, 0.5 mm pitch —
Lead Finish Matte Tin (lead-free) —
동작 온도 -40C to +85C (Industrial) [DATA_NEEDED: Operating temperature range]
MSL 레벨 3 (per JEDEC J-STD-020) [DATA_NEEDED: Moisture sensitivity level]
RoHS 상태 Compliant unknown
Configuration Pins DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE —
Compression Support Yes (reduces on-PROM footprint vs uncompressed bitstream) —
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
공급 전압 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
Lead-Free — unknown
실장 유형 — Surface Mount

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