EPC2L120N vs EPC2L20N 比較
詳細な並列比較: EPC2L120N メーカー: Intel および EPC2L20N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC2L120N | EPC2L20N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | Memory ICs |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.85 | $17.20 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | — |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| パッケージ | 84-pin PLCC (J-Lead) | — |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| 動作温度 | [DATA_NEEDED: industrial temp range] | 0C to +70C (commercial) |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| RoHS ステータス | unknown | Compliant |
| 機能 | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| メモリサイズ | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| パッケージ / ケース | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | — | Yes (multi-PROM chain via CE control) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| 実装タイプ | — | Surface Mount (J-Lead PLCC) |
| ピン数 | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| MSLレベル | — | 3 (168 hours) |